S70GL01GN00 Datasheet, PDF (12/83 Pages) SPANSION – 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit™ Process Technology

Advance Information
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels they
require, and the resulting output. The following subsections describe each of
these operations in further detail.
Table 1. Device Bus Operations
Operation
Read
Write (Program/Erase)
Accelerated Program
Standby
Output Disable
Reset
CE#
WE
WP#/
(Note 4) OE# # RESET# ACC
L
L
H
H
X
L
H
L
H
Note 2
L
H
L
H
V_HH
V_CC ±
0.3 V
X
X
V_CC ±
0.3 V
H
L
H
H
H
X
X
X
X
L
X
DQ8–DQ15
Addresses
(Note 1)
A_IN
A_IN
A_IN
DQ0– BYTE#
DQ7 = V_IH
D_OUT
D_OUT
(Note 3) (Note 3)
(Note 3) (Note 3)
BYTE#
= V_IL
DQ8–DQ14
= High-Z,
DQ15 = A-1
X
High-Z High-Z
High-Z
X
High-Z High-Z
High-Z
X
High-Z High-Z
High-Z
Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID = 11.5–12.5 V, V_HH = 11.5–12.5V, X = Don’t Care, SA = Sector
Address, A_IN = Address In, D_IN = Data In, D_OUT = Data Out
Notes:
1. Addresses are AMax:A0 in word mode; A_Max:A-1 in byte mode. Sector addresses are A_Max:A16 in both modes.
2. If WP# = V_IL, the first or last sector group remains protected. If WP# = V_IH, the first or last sector is protected or
unprotected as determined by the method described in “Write Protect (WP#)”. All sectors are unprotected when shipped
from the factory (The Secured Silicon Sector may be factory protected depending on version ordered.)
3. D_IN or D_OUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2, Figure 4, and
Figure 5).
4. CE# can be replaced with CE2# when referring to the second die in the package. CE# and CE2# must not be driven at the
same time.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or
word configuration. If the BYTE# pin is set at logic 1, the device is in word con-
figuration, DQ0–DQ15 are active and controlled by CE# or CE2# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data
I/O pins DQ0–DQ7 are active and controlled by CE# or CE2# and OE#. The data
I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# or CE2# and
OE# pins to V_IL. CE# or CE2# is the power control and selects the device. OE#
is the output control and gates array data to the output pins. WE# should remain
at V_IH.
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S70GL01GN00 MirrorBit^TM Flash
S70GL01GN00_00_A1 June 1, 2005