S70GL01GN00 Datasheet, PDF (79/83 Pages) SPANSION – 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit™ Process Technology

Advance Information
AC Characteristics
Alternate CE# Controlled Erase and Program Operations for Each S29GL512N
Parameter
Description
Speed Options
JEDEC Std.
(Note 6)
110
Unit
t_AVAV
t_AVWL
t_WC
t_AS
T_ASO
Write Cycle Time (Note 1)
Address Setup Time
Address Setup Time to OE# low during
toggle bit polling
110
0
15
t_ELAX
t_AH Address Hold Time
45
t_AHT
Address Hold Time From CE# or OE# high
during toggle bit polling
0
t_DVEH
t_DS Data Setup Time
t_EHDX
t_DH Data Hold Time
Min
t_CEPH CE# High during toggle bit polling
t_OEPH OE# High during toggle bit polling
t_GHEL
t_GHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
t_WLEL
t_EHWH
t_ELEH
t_EHEL
t_WS
t_WH
t_CP
t_CPH
WE# Setup Time
WE# Hold Time
CE# Pulse Width
CE# Pulse Width High
Write Buffer Program Operation (Note 2, and Note 3)
45
0
ns
20
0
35
30
240
Effective Write Buffer Program
Operation (Note 2, and 4)
t_WHWH1
t_WHWH1
Effective Accelerated Write Buffer
Program Operation (Notes 2, 4)
Per Word
Typ
Program Operation (Note 2)
Accelerated Programming Operation
(Note 2)
Word
15
13.5
µs
60
54
t_WHWH2 t_WHWH2 Sector Erase Operation (Note 2)
0.5
sec
Notes:
1. Not 100% tested.
2. See AC Characteristics‚ on page 69 for more information.
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Unless otherwise indicated, AC specifications for the 110 ns speed options are tested with V_IO = V_CC = 3 V.
6. CE# can be replaced with CE2# when referring to the second die in the package.
June 1, 2005 S70GL01GN00_00_A1
S70GL01GN00 MirrorBit^TM Flash
77