S70GL01GN00 Datasheet, PDF (52/83 Pages) SPANSION – 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit™ Process Technology

Advance Information
The Password Protection Command Set Entry command sequence must be
issued prior to any of the commands listed following to enable proper command
execution.
Note that issuing the Password Protection Command Set Entry command
disabled reads and writes the main memory.
„ Password Program Command
„ Password Read Command
„ Password Unlock Command
The Password Program command permits programming the password that is
used as part of the hardware protection scheme. The actual password is 64-bits
long. There is no special addressing order required for programming the pass-
word. The password is programmed in 8-bit or 16-bit portions. Each
portion requires a Password Program Command.
Once the Password is written and verified, the Password Protection Mode Lock Bit
in the Lock Register must be programmed in order to prevent verification. The
Password Program command is only capable of programming 0s. Programming a
1 after a cell is programmed as a 0 results in a time-out by the Embedded Pro-
gram Algorithm^TM with the cell remaining as a 0. The password is all F’s when
shipped from the factory. All 64-bit password combinations are valid as a
password.
The Password Read command is used to verify the Password. The Password is
verifiable only when the Password Protection Mode Lock Bit in the Lock Register
is not programmed. If the Password Protection Mode Lock Bit in the Lock Register
is programmed and the user attempts to read the Password, the device always
drives all F’s onto the DQ databus.
The lower two address bits (A1–A0) for word mode and (A1–A-1) for by byte
mode are valid during the Password Read, Password Program, and Password Un-
lock commands. Writing a 1 to any other address bits (A_MAX-A2) aborts the
Password Read and Password Program commands.
The Password Unlock command is used to clear the PPB Lock Bit to the unfreeze
state so that the PPB bits can be modified. The exact password must be entered
in order for the unlocking function to occur. This 64-bit Password Unlock com-
mand sequence takes at least 2 µs to process each time to prevent a hacker from
running through the all 64-bit combinations in an attempt to correctly match the
password. If another password unlock is issued before the 64-bit password check
execution window is completed, the command is ignored. If the wrong address
or data is given during password unlock command cycle, the device may enter
the write-to-buffer abort state. In order to exit the write-to-abort state, the write-
to-buffer-abort-reset command must be given. Otherwise the device hangs.
The Password Unlock function is accomplished by writing Password Unlock com-
mand and data to the device to perform the clearing of the PPB Lock Bit to the
unfreeze state. The password is 64 bits long. A1 and A0 are used for matching in
word mode and A1, A0, A-1 in byte mode. Writing the Password Unlock command
does not need to be address order specific. An example sequence is starting with
the lower address A1-A0=00, followed by A1-A0=01, A1-A0=10, and A1-A0=11
if the device is configured to operate in word mode.
Approximately 2 µs is required for unlocking the device after the valid 64-bit
password is given to the device. It is the responsibility of the microprocessor to
keep track of the entering the portions of the 64-bit password with the Password
Unlock command, the order, and when to read the PPB Lock bit to confirm suc-
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S70GL01GN00 MirrorBit^TM Flash
S70GL01GN00_00_A1 June 1, 2005