SP37E760 Datasheet, PDF (71/78 Pages) SMSC Corporation – 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS

AX
t19
nIOR
SD<7:0>
IOCHRDY
nWRITE
PD<7:0>
nDATASTB
nADDRSTB
nWAIT
t8
t3
t15
t13
t20
t11
t22
t12
t10
t5
t23
t4
t2
t21
Parameter
min
max
units
t2
nIOR Deasserted to Command Deasserted
t3
nWAIT Asserted to IOCHRDY Deasserted
t4
Command Deasserted to PDATA Hi-Z
t5
Command Asserted to PDATA Valid
t8
nIOR Asserted to IOCHRDY Asserted
t10
nWAIT Deasserted to nIOCHRDY Deasserted
t11
nIOCHRDY Deasserted to nIOR Deasserted
t12
nIOR Deasserted to SDATA High-Z (Hold Time)
t13
PData Valid to SDATA Valid
t15
Time Out
t19
Ax Valid to nIOR Asserted
t20
nIOR Deasserted to Ax Invalid
t21
Command Deasserted to nWAIT Deasserted
t22
nIOR Deasserted to nIOW or nIOR Asserted
t23
nIOR Asserted to Command Asserted
50
ns
0
40
ns
0
ns
0
ns
24
ns
50
ns
0
ns
0
40
ns
40
ns
10
12
µs
40
ns
10
ns
0
ns
40
ns
55
ns
NOTE:
1. nWRITE is controlled by setting the PDIR bit to "1" in the control register before
performing an EPP Read.
FIGURE 13 - EPP 1.7 DATA OR ADDRESS READ CYCLE
Notes
9.3.2 PARALLEL PORT ECP TIMING
9.3.2.1 Parallel Port FIFO (Mode 101)
The standard parallel port is run at or near the peak 500 Kbps allowed in the forward direction using DMA. The state
machine does not examine nAck and begins the next transfer based on Busy. Refer to FIGURE 14.
9.3.2.2 ECP Parallel Port Timing
The timing is designed to allow operation at approximately 2.0Mbytes/sec over a 15ft cable. If a shorter cable is used
then the bandwidth will increase.
9.3.2.3 Forward-Idle
When the host has no data to send it keeps HostClk (nStrobe) high and the peripheral will leave PeriphClk (Busy)
low.
SMSC DS – SP37E760
Page 71
Rev. 04/13/2001