SP37E760 Datasheet, PDF (67/78 Pages) SMSC Corporation – 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS

9.3.1 PARALLEL PORT EPP TIMING
AX
SD<7:0>
nIOW
IOCHRDY
nWRITE
PD<7:0>
nDATAST
nADDRSTB
nWAIT
t17
t8
t10
t13
t20
t1
t16
t3
t14
t15
t6
t18
t9
t12
t19
t11
t2
t5
t4
t7
Parameter
min
max
units
Notes
t1
nIOW Asserted to PDATA Valid
t2
nWAIT Asserted to nWRITE Change
t3
nWRITE to Command Asserted
t4
nWAIT Deasserted to Command Deasserted
t5
nWAIT Asserted to PDATA Invalid
t6
Time Out
t7
Command Deasserted to nWAIT Asserted
t8
SDATA Valid to IOW Asserted
t9
nIOW Deasserted to DATA Invalid
t10
nIOW Asserted to IOCHRDY Asserted
t11
WAIT Deasserted to nIOCHRDY Deasserted
t12
IOCHRDY Deasserted to nIOW Deasserted
t13
nIOW Asserted to nWRITE Asserted
t14
nWAIT Asserted to Command Asserted
t15
Command Asserted to nWAIT Deasserted
t16
PDATA Valid to Command Asserted
t17
Ax Valid to nIOW Asserted
t18
nIOW Deasserted to Ax Invalid
t19
nIOW Deasserted to nIOW or nIOR Asserted
t20
nWAIT Asserted to nWRITE Asserted
0
50
ns
60
185
ns
1
5
35
ns
60
190
ns
1
0
ns
1
10
12
µs
0
ns
10
ns
0
ns
0
24
ns
60
160
ns
1
10
ns
0
70
ns
60
210
ns
1
0
10
µs
10
ns
40
ns
10
ns
40
ns
60
185
ns
1
NOTE: WAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is considered to have settled
after it does not transition for a minimum of 50 nsec.
FIGURE 9 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE
SMSC DS – SP37E760
Page 67
Rev. 04/13/2001