SP37E760 Datasheet, PDF (61/78 Pages) SMSC Corporation – 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS

PARAMETER
O4 Type Buffer
Low Output Level
High Output Level
Output Leakage
OD12 Type Buffer
Low Output Level
Output Leakage
Supply Current Active
SYMBOL MIN TYP MAX UNITS
COMMENTS
V_OL
V_OH
2.4
I_OL
-10
0.4
V
I_OL = 4mA
V
I_OH = -2mA
+10
µA
V_IN = 0 to V_cc
(Note 1)
V_OL
0.4
V
I_OL = 12 mA
I_OL
-10
+10
µA
V_IN = 0 to V_cc
(Note 1)
I_CC
15 20
mA All outputs open.
Supply Current Standby
I_CSBY
100
µA Note 3
ChiProtect
I_IL
(SLCT, PE, BUSY, nACK,
nERROR)
±10 µA Chip in circuit:
V_CC = 0V
V_IN = 5.5V Max.
Backdrive Protect
I_IL
(nSLCTIN, nINIT, nAUTOFD,
nSTROBE, PD[7:0])
±10 µA Chip in circuit:
V_CC = 0V
V_IN = 5.5V Max.
Note 1: Output leakage is measured with the current pins in high impedance as defined by the PWRGD pin.
Note 2: Output leakage is measured with the low driving output off, either for a high level output or a high impedance
state defined by PWRGD.
Note 3: Defined by the device configuration with the PWRGD input low.
CAPACITANCE T_A = 25°C; fc = 1MHz; V_CC = 3.3V
Table 55 - Clock Pin Loading
PARAMETER
Clock Input Capacitance
Input Capacitance
Output Capacitance
SYMBOL
C_IN
LIMITS
MIN TYP MAX
20
C_IN
10
C_OUT
20
UNIT TEST CONDITION
pF
All pins except pin
under test tied to AC
ground
pF
pF
Table 56 - Capacitive Loading per Output Pin
SIGNAL NAME
TOTAL CAPACITANCE (pF)
SD[0:7]
240
IOCHRDY
240
IRQs
120
DRQs
120
TXD
100
nRTS
100
nDTR
100
PD[7:0]
240
nSLCTIN
240
nINIT
240
SMSC DS – SP37E760
Page 61
Rev. 04/13/2001