SP37E760 Datasheet, PDF (41/78 Pages) SMSC Corporation – 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS

a. When serviceIntr is “0”, dmaEn is “0”, direction is “0” and there are writeIntrThreshold or more free bytes in
the FIFO. Also, an interrupt is generated when serviceIntr is cleared to “0” whenever there are
writeIntrThreshold or more free bytes in the FIFO.
b.(1)When serviceIntr is 0, dmaEn is 0, direction is “1” and there are readIntrThreshold or more bytes in the
FIFO. Also, an interrupt is generated when serviceIntr is cleared to “0” whenever there are readIntrThreshold or
more bytes in the FIFO.
3. When nErrIntrEn is “0” and nFault transitions from high to low or when nErrIntrEn is set from “1” to “0” and
nFault is asserted.
4. When ackIntEn is “1” and the nAck signal transitions from a low to a high.
5.4.5.8 FIFO Operation
The FIFO threshold is set in the chip configuration registers. All data transfers to or from the parallel port can
proceed in DMA or Programmed I/O (non-DMA) mode as indicated by the selected mode. The FIFO is used by
selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. (FIFO test mode will be addressed separately.)
After a reset, the FIFO is disabled. Each data byte is transferred by a Programmed I/O cycle or PDRQ depending on
the selection of DMA or Programmed I/O mode.
The following paragraphs detail the operation of the FIFO flow control. In these descriptions, <threshold> ranges
from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15.
A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing
of the request for both read and write cases. The host must be very responsive to the service request. This is the
desired case for use with a “fast” system.
A high value of threshold (i.e. 12) is used with a “sluggish” system by affording a long latency period after a service
request, but results in more frequent service requests.
5.4.5.9 DMA TRANSFERS
Notes:
PDRQ - Currently selected Parallel Port DRQ channel
nPDACK - Currently selected Parallel Port DACK channel
PINTR - Currently selected Parallel Port IRQ channel
5.4.5.9.1 Typical DMA Mode Transfers
DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA services.
To use the DMA transfers, the host first sets up the direction and state as in the programmed I/O case. Then it
programs the DMA controller in the host with the desired count and memory address. Lastly it sets dmaEn to “1” and
serviceIntr to “0”. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA will empty
or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached,
an interrupt is generated and serviceIntr is asserted, disabling DMA. In order to prevent possible blocking of refresh
requests dReq shall not be asserted for more than 32 DMA cycles in a row. The FIFO is enabled directly by asserting
nPDACK and addresses need not be valid. PINTR is generated when a TC is received. PDRQ must not be
asserted for more than 32 DMA cycles in a row. After the 32^nd cycle, PDRQ must be kept unasserted until nPDACK
is deasserted for a minimum of 350nsec. (Note: The only way to properly terminate DMA transfers is with a TC).
DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting serviceIntr
to 1, followed by setting dmaEn to 0, and waiting for the FIFO to become empty or full.
Restarting the DMA is accomplished by enabling DMA in the host, setting dmaEn to 1, followed by setting
serviceIntr to 0.
5.4.5.9.2 DMA Mode - Transfers from the FIFO to the Host
(Note: In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer, even if the
chip continues to request more data from the peripheral).
The ECP activates the PDRQ pin whenever there is data in the FIFO. The DMA controller must respond to the
request by reading data from the FIFO. The ECP will deactivate the PDRQ pin when the FIFO becomes empty or
when the TC becomes true (qualified by nPDACK), indicating that no more data is required. PDRQ goes inactive
after nPDACK goes active for the last byte of a data transfer (or on the active edge of nIOR, on the last byte, if no
edge is present on nPDACK). If PDRQ goes inactive due to the FIFO going empty, then PDRQ is active again as
SMSC DS – SP37E760
Page 41
Rev. 04/13/2001