SP37E760 Datasheet, PDF (64/78 Pages) SMSC Corporation – 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS

X1K
nRESET
t1
t2
t2
t4
P a ra me te r
t1 ^{Clock CycleTime for 14.318MHZ}
t2 ^{Clock High Time/Low Time for}
14.318MHZ
t1 ^{Clock Cycle Time for 32KHZ}
t2 Clock High Time/Low Time for 32KHz
Clock Rise Time/Fall Time (not shown)
t4 _{nRESET Low Time}
min
typ
max units
70
65
ns
35
ns
us
31.25
us
16.53
5
ns
1.5
us
The nRESET low time is dependent upon the processor clock. The
nRESET must be active for a minimum of 24 x16MHz clock cycles.
FIGURE 6 - CLOCK TIMING
SMSC DS – SP37E760
Page 64
Rev. 04/13/2001