SP37E760 Datasheet, PDF (25/78 Pages) SMSC Corporation – 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS

BIT 2
Interrupt ID Bit
XMIT FIFO
Reset
Number of
Stop Bits
(STB)
OUT1
(Note 3)
Parity Error
(PE)
Trailing Edge
Ring Indicator
(TERI)
Bit 2
Bit 2
Bit 10
BIT 3
Interrupt ID Bit
(Note 5)
DMA Mode
Select (Note
6)
Parity Enable
(PEN)
OUT2
(Note 3)
Framing Error
(FE)
Delta Data
Carrier Detect
(DDCD)
Bit 3
Bit 3
Bit 11
BIT 4
0
Reserved
Even Parity
Select (EPS)
Loop
Break
Interrupt (BI)
Clear to
Send (CTS)
Bit 4
Bit 4
Bit 12
BIT 5
0
Reserved
Stick Parity
0
Transmitter
Holding
Register
(THRE)
Data Set
Ready
(DSR)
Bit 5
Bit 5
Bit 13
BIT 6
FIFOs Enabled
(Note 5)
RCVR Trigger
LSB
Set Break
0
Transmitter
Empty (TEMT)
(Note 2)
Ring Indicator
(RI)
Bit 6
Bit 6
Bit 14
BIT 7
FIFOs
Enabled (Note
5)
RCVR Trigger
MSB
Divisor Latch
Access Bit
(DLAB)
0
Error in
RCVR FIFO
(Note 5)
Data Carrier
Detect (DCD)
Bit 7
Bit 7
Bit 15
Note 3: This bit no longer has a pin associated with it.
Note 4: When operating in the XT mode, this register is not available.
Note 5: These bits are always zero in the non-FIFO mode.
Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip.
4.4 Notes On Serial Port FIFO Mode Operation
4.4.1 GENERAL
The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected.
4.4.2 TX AND RX FIFO OPERATION
The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx FIFO. The
UART will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the Tx FIFO will again be
enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely
autonomous operation of the Tx.
The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt whenever the Tx
FIFO is empty and the Tx interrupt is enabled, except in the following instance. Assume that the Tx FIFO is empty
and the CPU starts to load it. When the first byte enters the FIFO the Tx FIFO empty interrupt will transition from
active to inactive. Depending on the execution speed of the service routine software, the UART may be able to
transfer this byte from the FIFO to the shift register before the CPU loads another byte. If this happens, the Tx FIFO
will be empty again and typically the UART’s interrupt line would transition to the active state. This could cause a
system with an interrupt control unit to record a Tx FIFO empty condition, even though the CPU is currently servicing
that interrupt. Therefore, after the first byte has been loaded into the FIFO the UART will wait one serial
character transmission time before issuing a new Tx FIFO empty interrupt.
This one character Tx interrupt delay will remain active until at least two bytes have been loaded into the
FIFO, concurrently. When the Tx FIFO empties after this condition, the Tx interrupt will be activated without
a one character delay.
Rx support functions and operation are quite different from those described for the transmitter. The Rx FIFO receives
data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are
enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it holds 16 of
them. It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun
SMSC DS – SP37E760
Page 25
Rev. 04/13/2001