SP37E760 Datasheet, PDF (49/78 Pages) SMSC Corporation – 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS

7.3.3 CR02
CR02 can only be accessed in the configuration state and after the CSR has been initialized to 02H. The default
value of this register after power up is 88H (Table 27).
BIT NO.
0:2
3
4:6
7
BIT NAME
Reserved
UART1 Power Down¹
Reserved
UART2 Power Down¹
Table 27 - CR02
DESCRIPTION
Read Only. A read returns “0”.
A high level on this bit, allows normal operation of the Primary
Serial Port (Default). A low level on this bit places the Primary
Serial Port into Power Down Mode.
Read Only. A read returns “0”.
A high level on this bit, allows normal operation of the
Secondary Serial Port, including the SCE block (Default). A
low level on this bit places the Secondary Serial Port including
the SCE block into Power Down Mode.
Note¹:
Power Down bits disable the respective logical device and associated pins, however the power down bit
does not disable the selected address range for the logical device. To disable the host address registers the
logical device’s base address must be set below 100h. Devices that are powered down but still reside at a
valid I/O base address will participate in Plug-and-Play range checking.
7.3.4 CR03
CR03 can only be accessed in the configuration state and after the CSR has been initialized to 03H. The default
value after power up is 70H (Table 28).
BIT NO.
0
BIT NAME
PWRGD
1
Reserved
3
Reserved
4
Reserved
5
Reserved
6
Reserved
7,2
ADRx/
IRQ_B
Table 28 - CR03
DESCRIPTION
Bit 0 Pin Function
0
PWRGD (default)
1
Reserved
Reserved- Read as Zero
Reserved - Read as zero
Reserved - Read as one
Reserved - Read as one
Reserved - Read as one
Bit - 7 Bit - 2 Pin 92
0
0
Default
0
1
Reserved
1
0
ADRX
1
1
IRQ_B
Note¹: See Note² in section CR05 on page 50.
SMSC DS – SP37E760
Page 49
Rev. 04/13/2001