SP37E760 Datasheet, PDF (56/78 Pages) SMSC Corporation – 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS

Table 44 - CR25: UART2 Base Address Register
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
ADR9
ADR8
ADR7
ADR6
ADR5
ADR4
ADR3
0
7.3.32 CR26
CR26 can only be accessed in the Configuration State and after the CSR has been initialized to 26H. The default
value of this register after power up is 00H (Table 45). CR26 is used to select the DMA for the Parallel Port (bits 0 -
3). Any unselected DMA Request output (DRQ) is in tristate.
Table 45 - CR26: PP DMA Selection Register
D3-D0
DMA SELECTED
0000
None
0001
DMA_A
0010
DMA_B
0011
DMA_C
7.3.33 CR27
CR27 can only be accessed in the configuration state and after the CSR has been initialized to 27H. The default
value of this register after power up is 00H (Table 46). CR27 is used to select the Parallel Port (bits 3 - 0). Any
unselected IRQ output (registers CR27 - CR29) is in tristate.
Table 46 - CR27: PP IRQ Selection Register
D3-D0
IRQ SELECTED
0000
None
0001
IRQ_A
0010
IRQ_B
0011
IRQ_C
0100
IRQ_D
0101
IRQ_E
0110
IRQ_F
0111
Reserved
1000
IRQ_H
7.3.34 CR28
CR28 can only be accessed in the configuration state and after the CSR has been initialized to 28H. The default
value of this register after power up is 00H. CR28 is used to select the IRQ for Serial Port 1 (bits 7 - 4) and for Serial
Port 2 (bits 3 - 0). Refer to the IRQ encoding for CR27 (Table 46). Any unselected IRQ output (registers CR27 -
CR29) is in tristate.
To properly share an IRQ between UART1 and UART2:
1. Configure UART1 to use the desired IRQ pin.
2. Set UART2 to 0FH i.e., set CR28.[3:0] = 1111b. This selects the share IRQ mechanism. Refer to Table 47,
below.
Table 47 - UART Interrupt Operation
UART1
UART2
IRQ PINS
UART1 UART1 IRQ UART2 UART2 IRQ Share UART1
OUT2 bit ^{Output State} OUT2 bit ^{Output State IRQ} Pin State
UART2
Pin State
0
Z
0
Z
No
Z
Z
1
asserted
0
Z
No
1
Z
1
de-asserted
0
Z
No
0
Z
0
Z
1
asserted
No
Z
1
0
Z
1
de-asserted
No
Z
0
1
asserted
1
asserted
No
1
1
SMSC DS – SP37E760
Rev. 04/13/2001