SP37E760 Datasheet, PDF (51/78 Pages) SMSC Corporation – 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS

7.3.8 CR07
CR07 can only be accessed in the configuration state and after the CSR has been initialized to 07H. The default
value of this register after power up is 00H (Table 30). CR07 controls auto power management.
BIT NO.
0,1
2
3
4
5
6
7
Table 30 - CR07: Auto Power Management and Boot Drive Select
BIT NAME
DESCRIPTION
Reserved Read as 0.
Reserved Read as 0.
Reserved Read as 0.
Parallel Port
Enable
UART 2 Enable
UART 1 Enable
Reserved
This bit controls the AUTOPOWER DOWN feature of the Parallel Port.
The function is:
0 = Auto powerdown disabled (default)
1 = Auto powerdown enabled
This bit is reset to the default state by POR or a hardware reset.
This bit controls the AUTOPOWER DOWN feature of the UART2.
The function is:
0 = Auto powerdown disabled (default)
1 = Auto powerdown enabled
This bit is reset to the default state by POR or a hardware reset.
This bit controls the AUTOPOWER DOWN feature of the UART1.
The function is:
0 = Auto powerdown disabled (default)
1 = Auto powerdown enabled
This bit is reset to the default state by POR or a hardware reset.
Read as 0.
7.3.9 CR08
CR08 can only be accessed in the configuration state and after the CSR has been initialized to 08H. The default
value of this register after power up is 00H (Table 31). CR08 contains the lower 4 bits (ADRA7:4) for the ADRx
address decoder. Bits D0 - D3 are Reserved. Reserved bits cannot be written and return 0 when read.
Table 31 - CR08: ADRx Lower Address Decode
D7
D6
D5
D4
D3
D2
D1
D0
ADRA7 ADRA6 ADRA5 ADRA4
Reserved
7.3.10 CR09
CR09 can only be accessed in the configuration state and after the CSR has been initialized to 09H. The default
value of this register after power up is 00H (Table 32). CR09 contains the upper 3 bits (ADRA10:8) of the ADRx
address decoder and the ADRx Configuration Control Bits D[7:6]. The ADRx Configuration Control Bits configure the
ADRx Address Decoder (Table 33).
Table 32 - CR09: ADRx Upper Address Decoder and Configuration
D7
D6
D5
D4
D3
D2
D1
ADRx
CONFIGURATION
Reserved
ADRA10 ADRA9
CONTROL
D0
ADRA8
SMSC DS – SP37E760
Page 51
Rev. 04/13/2001