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SP37E760 Datasheet, PDF (19/78 Pages) SMSC Corporation – 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS | |||
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4.1.6.3 Parity Enable, Bit 3
When the Parity Enable bit is a logic â1â a parity bit is generated (transmit data) or checked (receive data) between
the last data word bit and the first stop bit of the serial data. The parity bit is used to generate an even or odd number
of 1s when the data word bits and the parity bit are summed.
4.1.6.4 Even Parity Select, Bit 4
When the Even Parity Select (EPS) bit is a logic â0â and the Parity Enable is a logic â1â, an odd number of logic â1ââs
is transmitted or checked in the data word and the parity bit. When the Parity Enable is a logic â1â and the EPS bit is
a logic â1â an even number of bits is transmitted and checked.
4.1.6.5 Stick Parity, Bit 5
When the Stick Parity bit is a logic â1â and the Parity Enable is a logic â1â, the parity bit is transmitted and then
detected by the receiver in the opposite state indicated by the EPS bit.
4.1.6.6 Set Break, Bit 6
When the Set Break Control bit is a logic â1â, the transmit data output (TXD) is forced to the Spacing or logic â0â state
and remains there until reset by a low level bit 6, regardless of other transmitter activity. This feature enables the
Serial Port to alert a terminal in a communications system.
4.1.6.7 DLAB, Bit 7
The Divisor Latch Access Bit must be set high (logic â1â) to access the Divisor Latches of the Baud Rate Generator
during read or write operations. It must be set low (logic â0â) to access the Receiver Buffer Register, the Transmitter
Holding Register, or the Interrupt Enable Register.
4.1.7 MODEM CONTROL REGISTER (MCR)
The Modem Control register (Address Offset = 4H, DLAB = X, READ/WRITE) manages the interface for the MODEM,
data set, or device emulating a MODEM.
4.1.7.1 Data Terminal Ready, Bit 0
The Data Terminal Ready bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic â1â,
the nDTR output is forced to a logic â0â. When bit 0 is a logic â0â, the nDTR output is forced to a logic â1â.
Request To Send, Bit 1
The Request To Send bit controls the Request To Send (nRTS) output. . When bit 1 is set to a logic â1â, the
nRTS output is forced to a logic â0â. When bit 1 is a logic â0â, the nRTS output is forced to a logic â1â.
4.1.7.2 OUT1, Bit 2
The OUT1 bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or written
by the CPU.
4.1.7.3 OUT2, Bit 3
The OUT2 bit is used to enable the UART interrupt. When OUT2 is a logic â0â, the serial port interrupt output is
forced to a high impedance state; i.e, disabled. When OUT2 is a logic â1â, the serial port interrupt outputs are
enabled.
4.1.7.4 Loop, Bit 4
The Loop bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic â1â, the
following occurs:
1. The TXD is set to the Marking State (logic â1â).
2. The receiver Serial Input (RXD) is disconnected.
3. The output of the Transmitter Shift Register is âlooped backâ into the Receiver Shift Register input.
4. All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are disconnected.
5. The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the four
MODEM Control inputs (nDSR, nCTS, RI and DCD) respectively.
6. The Modem Control output pins are forced inactive.
7. Data that is transmitted is immediately received.
SMSC DS â SP37E760
Page 19
Rev. 04/13/2001
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