SP37E760 Datasheet, PDF (17/78 Pages) SMSC Corporation – 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS

FIFO
MODE
ONLY
BIT
3
0
0
INTERRUPT
IDENTIFICATION
REGISTER
BIT BIT BIT
21
0
00
1
11
0
0
10
0
1
10
0
0
01
0
0
00
0
Table 5 - Interrupt Control
INTERRUPT SET AND RESET FUNCTIONS
PRIORITY
LEVEL
-
Highest
Second
Second
Third
Fourth
INTERRUPT INTERRUPT
INTERRUPT
TYPE
SOURCE RESET CONTROL
None
Receiver Line
Status
Received
Data
Available
Character
Time-out
Indication
Transmitter
Holding
Register
Empty
MODEM
Status
None
-
Overrun Error,
Parity Error,
Framing Error
or Break
Interrupt
Reading the Line
Status Register
Receiver Data
Available
Read Receiver
Buffer or the FIFO
drops below the
trigger level.
No Characters Reading the
Have Been
Receiver Buffer
Removed
Register
From or Input
to the RCVR
FIFO during
the last 4
Character
times and there
is at least 1
character in it
during this time
Transmitter
Reading the IIR
Holding
Register (if Source
Register Empty of Interrupt) or
Writing the
Transmitter Holding
Register
Clear to Send
or Data Set
Ready or Ring
Indicator or
Data Carrier
Detect
Reading the
MODEM Status
Register
4.1.5 FIFO CONTROL REGISTER (FCR)
The FIFO Control register (Address Offset = 2H, DLAB = X, WRITE) appears at the same location as the IIR. This
register is used to enable and clear the FIFOs and set the RCVR FIFO trigger level. Note: DMA is not supported.
4.1.5.1 FIFO Enable, Bit 0
Setting the FIFO Enable bit to a logic “1” enables both the XMIT and RCVR FIFOs. Clearing this bit to a logic “0”
disables both the XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO Mode to
non-FIFO (16450) mode, data is automatically cleared from the FIFOs. This bit must be a 1 when other bits in this
register are written to or they will not be properly programmed.
4.1.5.2 RCVR FIFO Reset, Bit 1
Setting the RCVR FIFO Reset bit to a logic “1” clears all bytes in the RCVR FIFO and resets its counter logic
to 0. The shift register is not cleared. This bit is self-clearing.
4.1.5.3 XMIT FIFO Reset, Bit 2
Setting the XMIT FIFO Reset bit to a logic “1” clears all bytes in the XMIT FIFO and resets its counter logic to 0. The
shift register is not cleared. This bit is self-clearing.
SMSC DS – SP37E760
Page 17
Rev. 04/13/2001