SP37E760 Datasheet, PDF (24/78 Pages) SMSC Corporation – 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS

1. Bit 0=1 as long as there is one byte in the RCVR FIFO.
2. Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as when in
the interrupt mode, the IIR is not affected since EIR bit 2=0.
3. Bit 5 indicates when the XMIT FIFO is empty.
4. Bit 6 indicates that both the XMIT FIFO and shift register are empty.
5. Bit 7 indicates whether there are any errors in the RCVR FIFO.
There is no trigger level reached or time-out condition indicated in the FIFO Polled Mode, however, the RCVR and
XMIT FIFOs are still fully capable of holding characters.
REGISTER
ADDRESS*
ADDR = 0
DLAB = 0
ADDR = 0
DLAB = 0
ADDR = 1
DLAB = 0
ADDR = 2
Table 11 - Individual UART Channel Register Summary
REGISTER NAME
REGISTER
SYMBOL
BIT 0
BIT 1
Receive Buffer Register
(Read Only)
RBR
Data Bit 0 (Note Data Bit 1
1)
Transmitter Holding
Register (Write Only)
THR
Data Bit 0
Data Bit 1
Interrupt Enable Register
Interrupt Ident. Register
(Read Only)
IER
Enable Received Enable Transmitter
Data Available
Holding Register
Interrupt (ERDAI) Empty Interrupt
(ETHREI)
IIR
”0” if Interrupt
Interrupt ID Bit
Pending
ADDR = 2
ADDR = 3
FIFO Control Register
(Write Only)
Line Control Register
ADDR = 4 MODEM Control Register
FCR
LCR
MCR
FIFO Enable
Word Length
Select Bit 0
(WLS0)
Data Terminal
Ready (DTR)
RCVR FIFO Reset
Word Length
Select Bit 1
(WLS1)
Request to Send
(RTS)
ADDR = 5
ADDR = 6
Line Status Register
MODEM Status Register
LSR
MSR
Data Ready (DR)
Delta Clear to
Send (DCTS)
Overrun Error (OE)
Delta Data Set
Ready (DDSR)
ADDR = 7 Scratch Register (Note 4)
SCR
Bit 0
Bit 1
ADDR = 0 Divisor Latch (LS)
DDL
Bit 0
Bit 1
DLAB = 1
ADDR = 1 Divisor Latch (MS)
DLM
Bit 8
Bit 9
DLAB = 1
*DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
Table 12 - Individual UART Channel Register Summary Continued
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
Data Bit 2
Data Bit 3
Data Bit 4 Data Bit 5 Data Bit 6
Data Bit 7
Data Bit 2
Data Bit 3
Data Bit 4 Data Bit 5 Data Bit 6
Data Bit 7
Enable
Enable
0
0
0
0
Receiver Line MODEM
Status
Status
Interrupt
Interrupt
(ELSI)
(EMSI)
SMSC DS – SP37E760
Page 24
Rev. 04/13/2001