SP37E760 Datasheet, PDF (20/78 Pages) SMSC Corporation – 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS

The Loopback feature allows the processor to verify the transmit and receive data paths of the Serial Port. The
receiver and the transmitter interrupts are fully operational in loopback mode. The MODEM Control Interrupts are
also operational but the interrupts’ sources are now the lower four bits of the MODEM Control Register instead of the
MODEM Control inputs.
The interrupts are still controlled by the Interrupt Enable Register.
4.1.7.5 Reserved, Bits 5 - 7
Bits 5 to 7 are RESERVED. Reserved bits cannot be written and return 0 when read.
4.1.8 LINE STATUS REGISTER (LSR)
Address Offset = 5H, DLAB = X, READ/WRITE
4.1.8.1 Data Ready, Bit 0
Data Ready (DR) is set to a logic “1” whenever a complete received data character has been transferred into the
Receiver Buffer Register or the FIFO. DR is reset to a logic “0” by reading all of the data in the Receive Buffer
Register or the FIFO.
4.1.8.2 Overrun Error, Bit 1
The Overrun Error (OE) bit indicates that data in the Receiver Buffer Register was not read before the next character
was transferred into the register, thereby destroying the previous character. In FIFO mode, an overrun error will occur
only when the FIFO is full and the next character has been completely received in the shift register: the character in
the shift register is overwritten but not transferred to the FIFO. The OE indicator is set to a logic “1” immediately upon
detection of an overrun condition and reset whenever the Line Status Register is read.
4.1.8.3 Parity Error, Bit 2
The Parity Error (PE) bit indicates that the received data character does not have the correct even or odd parity, as
selected by the even parity select bit. The PE is set to a logic “1” upon detection of a parity error and is reset to a
logic “0” whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular
character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO.
4.1.8.4 Framing Error, Bit 3
The Framing Error (FE) bit indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic “1”
whenever the stop bit following the last data bit or parity bit is detected as a zero bit (Spacing level). The FE is reset
to a logic “0” whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular
character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO.
The Serial Port will try to resynchronize after a framing error. To do this, it assumes that the framing error was due to
the next start bit, so it samples this ‘start’ bit twice and then takes in the ‘data’.
4.1.8.5 Break Interrupt, Bit 4
The Break Interrupt (BI) bit is set to a logic “1” whenever the received data input is held in the Spacing state (logic
“0”) for longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop
bits). The BI is reset after the CPU reads the contents of the Line Status Register. In the FIFO mode this error is
associated with the particular character in the FIFO it applies to. This error is indicated when the associated character
is at the top of the FIFO. When break occurs only one zero character is loaded into the FIFO. Restarting after a
break is received requires the serial data (RXD) to be logic “1” for at least ½ bit time.
Note: LSR Bits 1 through 4 produce a Receiver Line Status Interrupt whenever any of the corresponding conditions
are detected and the interrupt is enabled.
4.1.8.6 Transmitter Holding Register Empty, Bit 5
The Transmitter Holding Register Empty (THRE) bit indicates that the Serial Port is ready to accept a new character
for transmission. In addition, this bit causes the Serial Port to issue an interrupt when the Transmitter Holding
Register interrupt enable is set high. The THRE bit is set to a logic “1” when a character is transferred from the
Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic “0” whenever the CPU loads
the Transmitter Holding Register. In the FIFO mode this bit is set when the XMIT FIFO is empty, it is cleared when at
least 1 byte is written to the XMIT FIFO. Bit 5 is read-only.
SMSC DS – SP37E760
Page 20
Rev. 04/13/2001