SP37E760 Datasheet, PDF (70/78 Pages) SMSC Corporation – 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS

AX
SD<7:0>
nIOW
IO C H RDY
nWRITE
PD<7:0>
nDATAST
nADDRSTB
nWAIT
t17
t8
t10
t20
t13
t1
t16
t3
t18
t9
t6
t12
t19
t11
t2
t5
t4
t21
Parameter
min
max
units
N ote s
t1
nIOW Asserted to PDATA Valid
t2
Command Dessserted to nWRITE Change
t3
nWRITE to Command
t4
nIOW Deasserted to Command Deasserted
t5
Command Deasserted to PDATA Invalid
t6
Time Out
t8
SDATA Valid to nIOW Asserted
t9
nIOW Deasserted to DATA Invalid
t10
nIOW Asserted to IOCHRDY Asserted
t11
nWAIT Deasserted to IOCHRDY Deasserted
t12
IOCHRDY Deasserted to nIOW Deasserted
t13
nIOW Asserted to nWRITE Asserted
t16
PDATA Valid to Command Asserted
t17
Ax Valid to nIOW Asserted
t18
nIOW Deasserted to Ax Invalid
t19
nIOW Deasserted to nIOW or nIOR Asserted
t20
nWAIT Asserted to IOCHRDY Deasserted
t21
Command Deasserted to nWAIT Deasserted
0
50
ns
0
40
ns
5
35
ns
50
ns
2
50
ns
10
12
µs
10
ns
0
ns
0
24
ns
40
ns
10
ns
0
50
ns
10
35
ns
40
ns
10
µs
100
ns
45
ns
0
ns
NOTES:
1. WRITE is controlled by clearing the PDIR bit to "0" in the control register before
performing an EPP W rite.
2. This number is only valid if WAIT is active when nIOW goes active.
FIGURE 12 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE
SMSC DS – SP37E760
Page 70
Rev. 04/13/2001