SP37E760 Datasheet, PDF (26/78 Pages) SMSC Corporation – 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS

Error flag. Normally, the FIFO depth and the programmable trigger levels will give the CPU ample time to empty the
Rx FIFO before an overrun occurs.
One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level in the
FIFO. This could occur when data at the end of the block contains fewer bytes than the trigger level. No interrupt
would be issued to the CPU and the data would remain in the UART. To prevent the software from having to
check for this situation the chip incorporates a time-out interrupt.
The time-out interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU nor the Rx shift
register has accessed the Rx FIFO within 4 character times of the last byte. The time-out interrupt is cleared or reset
when the CPU reads the Rx FIFO or another character enters it.
These FIFO related features allow optimization of
CPU/UART transactions and are especially useful given
the higher baud rate capability (256K baud).
SMSC DS – SP37E760
Page 26
Rev. 04/13/2001