C541U_99 Datasheet, PDF (96/192 Pages) Siemens Semiconductor Group – 8-BIT CMOS MICROCONTROLLER

On-Chip Peripheral Components
C541U
6.4.5 Initialization of USB Module
After a hardware reset operation bits PCLK, SPEED, and UCLK are set to 0. If full speed operation
is required, a well defined procedure must be executed for switching on the clock for the USB
module :
– USB PLL is switched on by setting bit PCLK
waiting 3 ms for PLL being locked
setting bit UCLK
This switch-on procedure after a hardware reset assures a proper operation of the USB clock
system. When the USB clock system is switched on, a software initialization procedure must follow
This procedure must execute the following steps :
– Setting bit SWR in register DCR starts the software reset operation for the complete USB
module. Bit SPEED must be set together with SWR in the same instruction (write protection
of SPEED bit).
– When the software reset is finished, bit SWR is cleared by hardware and bit DINIT is set to
indicate the start of the initialization sequence.
– The USB module must be functionally initialized from the CPU by writing five configuration
bytes for each endpoint to the USBVAL register. Thereafter, bit DONE0 in register EPBS0
must be set by software.
Figure 6-33 shows the 5-byte configuration block which must be transmitted by the CPU to the USB
module via the USBVAL register for each endpoint. The gray shaded fields have a fixed “0“ or “1“
value for each endpoint while the white bitfields have to be filled by parameters according table 6-6.
Byte 0
0
Byte 1
0
Byte 2
Byte 3
0
Byte 4
0
EPNum
0
EPType
0
1
EPDir msb
0
0
EPPackSize
EPPackSize
lsb
0
0
0
0
0
EPNum
0
0
0
0
0
0
0
Constant data for each USB configuration block
Figure 6-33
USB Configuration Block
The five byte USB configuration block must be transfered sequentially (byte 0 to byte 4) from the
CPU to the USB module for each endpoint beginning with endpoint 0, followed by the USB
configuration block for endpoint 1 and so on up to the USB configuration block for endpoint 4.
EPNum is set to 000B, 001B, .... up to 100B for endpoints 0 up to 4. After this action, bit DINIT is
reset by hardware and the software reset and initialization sequence are finished.
Semiconductor Group
6-51
1999-04-01