C541U_99 Datasheet, PDF (111/192 Pages) Siemens Semiconductor Group – 8-BIT CMOS MICROCONTROLLER

On-Chip Peripheral Components
C541U
6.4.7.3 Endpoint Registers
Each of the five endpoints has its own endpoint register set which contains the following registers
(n=0-4) :
– EPBCn Endpoint n Buffer Control Register
– EPBSn Endpoint n Buffer Status Register
– EPIERn Endpoint n Interrupt Enable Register
– EPIRRn Endpoint n Interrupt Request Register
– EPBAn Endpoint n Base Address Register
– EPLENn Endpoint n Buffer Length Register
The endpoint buffer control registers control the endpoint specific operations.
Endpoint 1 Buffer Control RegisterEPBCn, n=0-4 (Address C1H)
Bit No. MSB
7
6
5
4
3
2
1
C1H STALLn 0
rw
r
0 GEPIEn SOFDEn INCEn 0
r
rw
rw
rw
r
Reset Value : 00H
LSB
0
DBMn EPBCn
rw
Bit
STALLn
GEPIEn
SOFDEn
0
Function
Endpoint stall
Bit STALL can be set to indicate that the endpoint is stalled.
If STALL=0, the endpoint n is active.
If STALL=1, the endpoint n is stalled.
Note : If the stall bit for endpoint 0 (STALL0) is set, the next incoming setup token
will automatically clear it.
Global endpoint interrupt enable
Bit GEPIEn enables or disables the generation of the global endpoint interrupt n
based on the endpoint specific interrupt request bits in register EPIRn.
If GEPIE=0, the USB endpoint n interrupt is disabled.
If GEPIE=1, the USB endpoint n interrupt is enabled.
Start of frame done enable
If bit SOFDE is set, the current CPU buffer in USB memory is automatically tagged
full (data flow from the CPU to the USB) or empty (data flow from the USB to the
CPU) on each detection of a start of frame on the USB (auto-done).
If SOFDE=0, no action on SOF.
If SOFDE=1, the automatical generation of DONE on SOF is enabled.
Reserved for future use. For compatiblity, these bits have to be ignored in all read
accesses and written with zero in all write accesses.
Semiconductor Group
6-66
1999-04-01