C541U_99 Datasheet, PDF (157/192 Pages) Siemens Semiconductor Group – 8-BIT CMOS MICROCONTROLLER

Fail Safe Mechanisms
C541U
8.1.1 Input Clock Selection
The input clock rate of the watchdog timer is derived from the system clock of the C541U. There is
a prescaler available, which is software selectable and defines the input clock rate. This prescaler
is controlled by bit WDTPSEL in the SFR WDTREL. Tabel 8-1 shows resulting timeout periods at
f_OSC = 12 MHz.
Special Function Register WDTREL (Address 86H)
Reset Value : 00H
MSB
LSB
Bit No. 7
6
5
4
3
2
1
0
86H
WDT
PSEL
Reload Value
WDTREL
Bit
WDTPSEL
WDTREL.6 - 0
Function
Watchdog timer prescaler select bit.
If WDTPSEL=0, the watchdog timer is clocked by f_OSC/12 (default after
reset).
If WDTPSEL=1, the watchdog timer is clocked by f_OSC/192
Seven bit reload value
for the high-byte of the watchdog timer. This value is loaded to WDTH
when a refresh is triggered by a consecutive setting of bits WDT and
SWDT.
Immediately after start, the watchdog timer is initialized to the reload value programmed to
WDTREL.0-WDTREL.6. After an external hardware reset, an oscillator watchdog power on reset,
or a watchdog timer reset, register WDTREL is cleared to 00H. The lower seven bits of WDTREL
can be loaded by software at any time.
Table 8-1
Watchdog Timer Time-Out Periods (WDTPSEL = 0)
WDTREL
00H
80H
7FH
Time-Out Period
f_OSC = 12 MHz
32.768 ms
0.55 s
256 µs
Comments
This is the default value
Maximum time period
Minimum time period
Semiconductor Group
8-2
1997-10-01