C541U_99 Datasheet, PDF (107/192 Pages) Siemens Semiconductor Group – 8-BIT CMOS MICROCONTROLLER

On-Chip Peripheral Components
C541U
The device interrupt enable register DIER contains the enable bits for the different types of device
interrupts. With these bits, the device interrupts can be individually enabled or disabled. The general
device interrupt enable bit EUDI is located in SFR IEN1. A device interrupt can be only generated
if EUDI and EA (global interrupt enable bit in IEN0) are set too.
USB Device Interrupt Enable Register DIER (Address C3H)
Bit No.
C3H
MSB
7
SE0IE
rw
6
DAIE
rw
5
DDIE
rw
4
SBIE
rw
3
SEIE
rw
2
STIE
rw
1
SUIE
rw
Reset Value : 00H
LSB
0
SOFIE DIER
rw
Bit
SE0IE
DAIE
DDIE
SBIE
SEIE
STIE
Function
Single ended zero Interrupt Enable
Setting bit SE0IE enables the generation of a device interrupt each time a single
ended zero is detected for more than 2.5µs (reset by host, not EOP).
If SE0IE=0, the single ended zero interrupt is disabled.
If SE0IE=1, the single ended zero interrupt is enabled.
Device attached interrupt enable
Setting bit DAIE enables the generation of a device interrupt when it is attached
to the USB bus.
If DAIE=0, the device attached interrupt is disabled.
If DAIE=1, the device attached interrupt is enabled.
Device detached interrupt enable
Setting bit DDIE enables the generation of a device interrupt when it is detached
from the USB bus.
If DDIE=0, the device detached interrupt is disabled.
If DDIE=1, the device detached interrupt is enabled.
Suspend begin interrupt enable
Setting bit SBIE enables the generation of a device interrupt if bit SBI is set, this
means the suspend mode is entered.
If SBIE=0, the suspend begin interrupt is disabled.
If SBIE=1, the suspend begin interrupt is enabled.
Suspend change interrupt enable
Setting bit SEIE enables the generation of a device interrupt if bit SEI is set, this
means the suspend mode is left.
If SEIE=0, the suspend change interrupt is disabled.
If SEIE=1, the suspend change interrupt is enabled.
Status interrupt enable
Bit STIE enables the generation of a device interrupt at the end of the status phase
of a control transfer.
If STIE=0, the status interrupt is disabled.
If STIE=1, the status interrupt is enabled.
Semiconductor Group
6-62
1999-04-01