C541U_99 Datasheet, PDF (115/192 Pages) Siemens Semiconductor Group – 8-BIT CMOS MICROCONTROLLER

On-Chip Peripheral Components
C541U
The endpoint interrupt enable registers contain the endpoint specific interrupt enable bits. With
these bits, the endpoint specific interrupts can be individually enabled or disabled. Additionally to a
bit in an EPIEn register, the global interrupt bit EPIn in GEPIR for endpoint n and the general
endpoint interrupt bit EUEI in IEN1 and the general interrupt enable bit EA in IEN0 must be set for
the interrupt becoming active.
Endpoint Interrupt Enable Register EPIEn, n=0-4 (Address C3H)
Reset Value : 00H
Bit No. MSB
LSB
7
6
5
4
3
2
1
0
C3H
AIEn NAIEn RLEIEn 0 DNRIEn NODIEn EODIEn SODIEn EPIEn
rw
rw
rw
rw
rw
rw
rw
rw
For accessing EPIEn, SFR EPSEL must be 0nH.
Bit
AIEn
NAIEn
RLEIEn
0
DNRIEn
NODIEn
Function
USB acknowledge interrupt enable
Bit AIEn enables the generation of an endpoint specific acknowledge interrupt
when bit ACKn in register EPIRn is set.
If AIEn=0, the USB acknowledge interrupt is disabled.
If AIEn=1, the USB acknowledge interrupt is enabled.
USB not acknowledged interrupt enable
Bit NAIEn enables the generation of an endpoint specific not acknowledged
interrupt when bit NACKn in register EPIRn is set.
If NAIEn=0, the USB not acknowledged interrupt is disabled.
If NAIEn=1, the USB not acknowledged interrupt is enabled.
Read length error interrupt enable
Bit RLEIEn enables the generation of an endpoint specific read length error
interrupt when bit RLEn in register EPIRn is set.
If RLEIEn=0, the read length error interrupt is disabled.
If RLEIEn=1, the read length error interrupt is enabled.
Reserved for future use. For compatiblity, these bits have to be ignored in all read
accesses and written with zero in all write accesses.
Data not ready interrupt enable
Bit DNRIEn enables the generation of an endpoint specific data not ready interrupt
when bit DNRn in register EPIRn is set.
If DNRIEn=0, the data not ready interrupt is disabled.
If DNRIEn=1, the data not ready interrupt is enabled.
No data interrupt enable
Bit NODIEn enables the generation of an endpoint specific no data interrupt when
bit NODn in register EPIRn is set.
If NODIEn=0, the no data interrupt is disabled.
If NODIEn=1, the no data interrupt is enabled.
Semiconductor Group
6-70
1999-04-01