C541U_99 Datasheet, PDF (184/192 Pages) Siemens Semiconductor Group – 8-BIT CMOS MICROCONTROLLER

OTP Memory Operation
C541U
condition is stored internally. After each 16th data byte the cumulated verify result (pass or fail) of
the last 16 verify operations is output at P3.5. This means that P3.5 stays at static level (low for fail
and high for pass) during the time when the following 16 bytes are checked. In OTP verification
mode, the C541U must be provided with a system clock at the XTAL pins.
Figure 10-9 shows an application example of a external circuitry which allows to verify a protected
OTP inside the. With RESET going inactive, the C541U starts the OTP verify sequence. Its ALE is
clocking an 14-bit address counter. This counter generates the addresses for an external EPROM
which is programmed with the content of the internal (protected) OTP. The verify detect logic
typically displays the state of the verify error output P3.5. P3.5 can be latched with the falling edge
of ALE.
When the last byte of the internal OTP has been handled, the C541U starts generating a PSEN
signal. This signal or the CY signal of the address counter indicate to the verify detect logic the end
of the internal OTP verification.
P3.5
ALE
2K
C540U
C541U
CY
CLK
12 / 13 - Bit
Address
Counter
R
Verify
Detect
Logic
A0 - A12
or
A0 - A11
RESET
&
V _CC
&
Compare
Code
ROM
Port 0
V _CC
EA
P2.7
PSEN
D0 - D7
CS OE
MCS03423
Figure 10-9
OTP Verification with Protection Level 1 - External Circuitry Example
Semiconductor Group
10-13
1997-10-01