C541U_99 Datasheet, PDF (166/192 Pages) Siemens Semiconductor Group – 8-BIT CMOS MICROCONTROLLER

Power Saving Modes
C541U
9.1 Idle Mode
In the idle mode the main oscillator of the C541U continues to run, but the CPU is gated off from the
clock signal. However, the interrupt system, the SSC, the USB module, and the timers with the
exception of the watchdog timer are further provided with the clock. The CPU status is preserved in
its entirety : the stack pointer, program counter, program status word, accumulator, and all other
registers maintain their data during idle mode.
The reduction of power consumption, which can be achieved by this feature depends on the number
of peripherals running. If all peripherals are disabled or stopped, the maximum power reduction can
be achieved. This state is also the test condition for the idle mode I_CC.
So the user has to take care which peripheral should continue to run and which has to be stopped
during idle mode. Also the state of all port pins – either the pins controlled by their latches or
controlled by their secondary functions – depends on the status of the controller when entering idle
mode.
Normally the port pins hold the logical state they had at the time idle mode was activated. If some
pins are programmed to serve their alternate functions they still continue to output during idle mode
if the assigned function is on. This applies to the serial interface in case it cannot finish reception or
transmission during normal operation. The control signals ALE and PSEN hold at logic high levels.
Table 9-1
Status of External Pins During Idle and Power-Down Mode
Outputs
ALE
PSEN
Port 0
Port 2
Port 1, 3
Last Instruction Executed from
Internal Code Memory
Idle
Power-Down
High
Low
High
Low
Data
Data
Data
Data
Data/alternate
outputs
Data/last output
Last Instruction Executed from
External Code Memory
Idle
Power-Down
High
Low
High
Low
Float
Float
Address
Data
Data/alternate
outputs
Data/last output
As in normal operation mode, the ports can be used as inputs during idle mode. Therefore, the
timers can be used to count external events, and external interrupts will be detected.
The idle mode is a useful feature which makes it possible to "freeze" the processor's status - either
for a predefined time, or until an external event reverts the controller to normal operation, as
discussed below. The watchdog timer is the only peripheral which is automatically stopped during
idle mode.
Semiconductor Group
9-3
1997-10-01