C541U_99 Datasheet, PDF (83/192 Pages) Siemens Semiconductor Group – 8-BIT CMOS MICROCONTROLLER

On-Chip Peripheral Components
C541U
Figure 6-21 shows more details of an USB write access to USB memory in single buffer mode. After
SOF(n) (start of frame) occured at 1 , the USB starts writing at 2 a fixed number of bytes into the
USB memory. A byte counter is incremented after every USB memory write operation. When the
USB memory write operation (Len(n)) is finished correctly, bit SOD (start of data) is set at 3 ,
indicating a full USB memory buffer. Furthermore, the byte counter value is stored in the
corresponding length register, indicating the number of bytes which have been transferred and can
be now read by the CPU. Subsequently, the CPU can read data bytes from USB memory,
generating an EOD (end of data) at 4 after the last byte has been read. Bit EOD set indicates an
empty USB buffer, which now can be written again by the USB.
Figure 6-21 also shows a second USB write access operation with a different number of bytes
(Len(n+1)), where the CPU read operation from the USB memory is interrupted twice.
Number of
Data Bytes
in USB Buffer
Len (n)
Len (n+1)
SOD
set
3
SOD
set
3
4
EOD
set
1
2
SOF (n)
set
USB write accesses
Frame n
12
SOF (n+1)
set
CPU read accesses
Frame n+1
Figure 6-21
Single Buffer Mode : Standard USB Write Access
4
EOD
set
Time
SOF (n+2)
set
MCT03401
Note: The CPU accesses shown in the following diagrams assume that bit INCE in the corres-
ponding endpoint control register is set.
A frame is the 1 ms time interval defined by the USB host.
Every frame begins with a SOF token (start-of-frame).
Semiconductor Group
6-38
1999-04-01