C541U_99 Datasheet, PDF (77/192 Pages) Siemens Semiconductor Group – 8-BIT CMOS MICROCONTROLLER

On-Chip Peripheral Components
C541U
Special Function Register SCF (Address ABH)
MSB
Bit No. 7
6
5
4
3
ABH
–
–
–
–
–
Reset Value : XXXXXX00B
LSB
2
1
0
– WCOL TC SCF
Bit
–
WCOL
TC
Function
Reserved for future use.
SSC write collision detect
If WCOL is set it indicates that an attempt was made to write to the shift register
STB while a data transfer was in progress and not fully completed. This bit will be
set at the trailing edge of the write signal during the erronous write attempt.
This bit can be reset in two different ways :
1. writing a "0" to the bit (bit access, byte access or read-modify-write access);
2. by reading the bit or the status register, followed by a write access to STB.
If bit WCEN in the SCIEN register is set, an interrupt request will be generated if
WCOL is set.
SSC transfer completed
If TC is set it indicates that the last transfer has been completed. It is set with the
last sample clock edge of a reception process.
This bit can be reset in two different ways:
1. writing a "0" to the bit (bit access, byte access or read-modify-write access)
after the receive buffer register SRB has been read;
2. by reading the bit or the status register, followed by a read access to SRB.
If bit TCEN in the SCIEN register is set, an interrupt request will be
generated if TC is set.
The register STB (at SFR address 94H) holds the data to be transmitted while SRB (at SFR address
95H) contains the data which was received during the last transfer. A write to the STB places the
data directly into the shift register for transmission. Only in master mode this also will initiate the
transmission/reception process. When a write collision occurs STB will hold the value written
erroneously. This value can be read by reading from STB.
A read from the receive buffer register SRB will transfer the data of the last transfer completed. This
register must be read before the next transmission completes or the data will be lost. There is no
indication for this overrun condition.
Semiconductor Group
6-32
1999-04-01