C541U_99 Datasheet, PDF (72/192 Pages) Siemens Semiconductor Group – 8-BIT CMOS MICROCONTROLLER

On-Chip Peripheral Components
C541U
6.3.6 Data/Clock Timing Relationships
The SSC provides four different clocking schemes for clocking the data in and out of the shift
register. Controlled by two bits in SSCCON, the clock polarity (idle state of the clock, control register
bit CPOL) and the clock/data relationship (phase control, control register bit CPHA), i.e. which clock
edges will be used for sample and shift. The following figures show the various possibilities.
6.3.6.1 Master Mode Operation
Figure 6-16 shows the clock/data/control relationship of the SSC in master mode. When CPHA is
set to 1, the MSB (or LSB) of the data that was written into the shift register will be provided on the
transmitter output after the first clock edge, the receiver input will sample with the next clock edge.
The direction (rising or falling) of the respective clock edge is depending on the clock polarity
selected. After the last bit has been shifted out, the data output STO will go to the high output level
(logic 1) and remain there until the next transmission is started. However, when enabling the SSC
after reset, the logic level of STO will be undefined, until the first transmission starts.
When CPHA is 0, the MSB (or LSB) will output immediately after the data was written into the shift
register. The first clock edge of SCLK will be used for sampling the input data, the next to shift out
the next bit. Between transmissons the data output STO will be "1".
SCLK
(CPOL = 0)
SCLK
(CPOL = 1)
Write to
STB Register
CPHA = 0
STO
Input Sample
at SRI
Write to
STB Register
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CPHA = 1
STO
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Input Sample
at SRI
1) MSB shift first mode is assumed (Bit LSBSM in register SCCMOD is 0)
Figure 6-16
Master Mode Operation of SSC
MCS02440
Semiconductor Group
6-27
1999-04-01