C541U_99 Datasheet, PDF (103/192 Pages) Siemens Semiconductor Group – 8-BIT CMOS MICROCONTROLLER

On-Chip Peripheral Components
C541U
The global endpoint interrupt request register GEPIRn (n=0-4) contaíns one flag for each endpoint
which indicates whether one or more of the eight endpoint specific interrupt requests have become
active. If a request flag in GEPIR is set, it is automatically cleared after a read operation of the
corresponding endpoint specific EPIRn register.
This register contains an additional device interrupt request flag at bit-7. This bit is not automatically
cleared by hardware, but has to be cleared by software. The rest of the device interrupt request
flags can be found in DIRR register.
USB Global Endpoint Interrupt Request Register GEPIR (Address D6H) Reset Value : 00H
Bit No. MSB
LSB
7
6
5
4
3
2
1
0
D6H DRVI
0
rw
r
0
EPI4 EPI3 EPI2 EPI1 EPI0 GEPIR
r
r
r
r
r
r
Bit
DRVI
0
EPI4
EPI3
EPI2
EPI1
EPI0
Function
Device request value interrupt
Bit DRVI is set each time the host sends device request that contains one or more
of the following :
- Configuration Value (through SET_CONFIGURATION device request)
- Alternate Setting (through SET_INTERFACE device request)
- Interface (through SET_INTERFACE device request)
This flag can only be cleared by writing ‘0’ to the bit. Writing ‘1’ to the bit will
be ignored. The device interrupt has to be enabled by bit DRVIE in DPWDR
(address E6_H).
Reserved for future use. For compatiblity, these bits have to be ignored in all read
accesses and written with zero in all write accesses.
Endpoint 4 interrupt request flag
If EPI4 is set, an endpoint 4 interrupt request is pending.
Endpoint 3 interrupt request flag
If EPI3 is set, an endpoint 3 interrupt request is pending.
Endpoint 2 interrupt request flag
If EPI2 is set, an endpoint 2 interrupt request is pending.
Endpoint 1 interrupt request flag
If EPI1 is set, an endpoint 1 interrupt request is pending.
Endpoint 0 interrupt request flag
If EPI0 is set, an endpoint 0 interrupt request is pending.
Bit 4 (GEPIEn) of the specific endpoint buffer control register EPBCn must be set if EPIn should
generate an interrupt. Additionally, bit EA (IEN0.7) and bit EUEI (IEN1.1) must be set when an
endpoint interrupt should be triggered.
Semiconductor Group
6-58
1999-04-01