C541U_99 Datasheet, PDF (159/192 Pages) Siemens Semiconductor Group – 8-BIT CMOS MICROCONTROLLER

Fail Safe Mechanisms
C541U
8.1.3 Starting the Watchdog Timer
The watchdog timer can be started by software (bit SWDT in SFR WDCON), but it cannot be
stopped during active mode of the device. If the software fails to clear the watchdog timer an internal
reset will be initiated. The reset cause (external reset or reset caused by the watchdog) can be
examined by software (status flag WDTS in WDCON is set). A refresh of the watchdog timer is done
by setting bits WDT (SFR WDCON) and SWDT consecutively. This double instruction sequence
has been implemented to increase system security.
It must be noted, however, that the watchdog timer is halted during the idle mode and power-down
mode of the processor (see section "Power Saving Modes"). Therefore, it is possible to use the idle
mode in combination with the watchdog timer function. But even the watchdog timer cannot reset
the device when one of the power saving modes has been entered accidentally.
8.1.4 Refreshing the Watchdog Timer
At the same time the watchdog timer is started, the 7-bit register WDTH is preset by the contents
of WDTREL.0 to WDTREL.6. Once started the watchdog timer cannot be stopped by software but
can be refreshed to the reload value only by first setting bit WDT (WDCON) and by the next
instruction setting SWDT (WDCON). Bit WDT will automatically be cleared during the third machine
cycle after having been set. This double-instruction refresh of the watchdog timer is implemented
to minimize the chance of an unintentional reset of the watchdog unit.
The reload register WDTREL can be written at any time, as already mentioned. Therefore, a
periodical refresh of WDTREL can be added to the above mentioned starting procedure of the
watchdog timer. Thus a wrong reload value caused by a possible distortion during the write
operation to WDTREL can be corrected by software.
Note : the watchdog timer registers WDTH and WDTL cannot be accessed by software.
8.1.5 Watchdog Reset and Watchdog Status Flag
If the software fails to clear the watchdog in time, an internally generated watchdog reset is entered
at the counter state 7FFCH. The duration of the reset signal then depends on the prescaler
selection (either 8 or 128 machine cycles). This internal reset differs from an external one in so far
as the watchdog timer is not disabled and bit WDTS is set. The WDTS is a flip-flop, which is set by
a watchdog timer reset and can be cleared by an external hardware reset. Bit WDTS allows the
software to examine from which source the reset was activated. The bit WDTS can also be cleared
by software.
Semiconductor Group
8-4
1997-10-01