S128 Datasheet, PDF (95/107 Pages) Renesas Technology Corp – Microcontroller

S128
2. Electrical Characteristics
Table 2.63 Data flash characteristics (2)
High-speed operating mode
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
Parameter
ICLK = 4 MHz
ICLK = 32 MHz
Symbol Min
Typ
Max
Min
Typ
Max
Unit
Programming time
1-byte
Erasure time
1-KB
Blank check time
1-byte
1-KB
Suspended time during erasing
Data flash STOP recovery time
t_DP1
-
t_DE1K
-
t_DBC1
-
t_DBC1K
-
t_DSED
-
t_DSTOP
5
52.4
8.98
-
-
-
-
463
-
286
-
24.3
-
1872
-
13.0
-
-
5
42.1
387
μs
6.42
237
ms
-
16.6
μs
-
512
μs
-
10.7
μs
-
-
μs
Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by
the software.
Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK
at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz
cannot be set.
Note 3. The frequency accuracy of ICLK must be ±3.5% during programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Table 2.64 Data flash characteristics (3)
Middle-speed operating mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V, Ta = –40 to +85°C
ICLK = 4 MHz
ICLK = 8 MHz
Parameter
Symbol Min
Typ
Max
Min
Typ
Max
Unit
Programming time
1-byte
Erasure time
1-KB
Blank check time
1-byte
1-KB
Suspended time during erasing
Data flash STOP recovery time
t_DP1
-
t_DE1K
-
t_DBC1
-
t_DBC1K
-
t_DSED
-
t_DSTOP
720
94.7
886
-
9.59
299
-
-
56.2
-
-
2.17
-
-
23.0
-
-
-
720
89.3
849
μs
8.29
273
ms
-
52.5
μs
-
1.51
ms
-
21.7
μs
-
-
ns
Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by
the software.
Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK
at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz
cannot be set.
Note 3. The frequency accuracy of ICLK must be ±3.5% during programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
2.13.3 Serial Wire Debug (SWD)
Table 2.65 SWD characteristics (1) (1 of 2)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
SWCLK clock cycle time
SWCLK clock high pulse width
SWCLK clock low pulse width
SWCLK clock rise time
SWCLK clock fall time
t_SWCKcyc
80
-
t_SWCKH
35
-
t_SWCKL
35
-
t_SWCKr
-
-
t_SWCKf
-
-
-
ns
Figure 2.69
-
ns
-
ns
5
ns
5
ns
R01DS0309EU0100 Rev.1.00
Mar 10, 2017
Page 95 of 107