S128 Datasheet, PDF (58/107 Pages) Renesas Technology Corp – Microcontroller

S128
2.3.6
2. Electrical Characteristics
I/O Ports, POEG, GPT, AGT, KINT, and ADC14 Trigger Timing
Table 2.30 I/O Ports, POEG, GPT, AGT, KINT, and ADC14 trigger timing
Parameter
I/O Ports
POEG
GPT
AGT
ADC14
KINT
Input data pulse width
Input/output data cycle (P002, P003, P010, P011)
POEG input trigger pulse width
Input capture pulse width
Single edge
Dual edge
AGTIO, AGTEE input cycle
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
AGTIO, AGTEE input high level
width, low-level width
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
AGTIO, AGTO, AGTOA, AGTOB
output frequency
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.4 V
Symbol Min
t_PRW
1.5
t_POcyc 10
t_POEW 3
t_GTICW 1.5
2.5
t_ACYC*¹ 250
500
1000
2000
t_ACKWH, 100
t_{ACKWL 200}
400
800
t_ACYC2
62.5
125
250
1.6 V ≤ VCC < 1.8 V
500
14-bit A/D converter trigger input pulse width
Key interrupt input low-level width
t_TRGW 1.5
t_KR
250
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Note 1. Constraints on AGTIO input: t_Pcyc × 2 (t_Pcyc: PCLKB cycle) < t_ACYC.
Unit
t_Pcyc
μs
t_Pcyc
t_PDcyc
Test
conditions
Figure 2.35
-
Figure 2.36
Figure 2.37
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t_Pcyc
ns
Figure 2.38
Figure 2.38
Figure 2.39
Figure 2.40
Port
t_PRW
Figure 2.35 I/O ports input timing
POEG input trigger
Figure 2.36 POEG input trigger timing
t_POEW
R01DS0309EU0100 Rev.1.00
Mar 10, 2017
Page 58 of 107