S128 Datasheet, PDF (67/107 Pages) Renesas Technology Corp – Microcontroller

S128
2. Electrical Characteristics
Table 2.36 SPI timing (2 of 2)
Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
Symbol
Min
Max
SPI
Data input setup
Master
t_SU
10
-
time
Slave
2.4V or above
10
-
1.8V or above
15
-
1.6V or above
20
-
Data input hold time Master
t_HF
0
-
(RSPCK is PCLKB/2)
Master
t_H
(RSPCK is not PCLKB/2)
t_Pcyc
-
SSL setup time
SSL hold time
Data output delay
Slave
Master
t_H
t_LEAD
Slave
Master
t_LAG
Slave
Master
2.7V or above t_OD
2.4V or above
20
-
– 30 + N x -
t_Spcyc*²
6 x t_Pcyc
-
– 30 + N x -
t_Spcyc*³
6 x t_Pcyc
-
-
14
-
20
1.8V or above
-
25
1.6V or above
-
30
Slave
2.7V or above
-
50
2.4V or above
-
60
1.8V or above
-
85
1.6V or above
-
110
Data output hold
time
Master
Slave
t_OH
0
-
0
-
Successive
transmission delay
MOSI and MISO
rise and fall time
Master
Slave
Output
t_TD
2.7V or above
2.4V or above
t_Dr, t_Df
t_SPcyc + 2 ×
t_Pcyc
6 × t_Pcyc
-
-
8 × t_SPcyc
+ 2 × t_Pcyc
-
10
15
1.8V or above
-
20
1.6V or above
-
30
Input
-
1
SSL rise and fall
Output 2.7V or above t_SSLr, t_SSLf
-
10
time
2.4V or above
-
15
1.8V or above
-
20
1.6V or above
-
30
Input
-
1
Slave access time
2.4V or above t_SA
-
2 × t_Pcyc
+100
1.8V or above
-
2 × t_Pcyc
+140
1.6V or above
-
2 × t_Pcyc
+180
Slave output release time
2.4V or above t_REL
-
2 × t_Pcyc
+100
1.8V or above
-
2 × t_Pcyc
+140
1.6V or above
-
2 × t_Pcyc
+180
R01DS0309EU0100 Rev.1.00
Mar 10, 2017
Unit^*1
ns
Test conditions
Figure 2.50 to
Figure 2.55
C = 30_PF
ns
ns
ns
ns
ns
ns
Figure 2.50 to
Figure 2.55
C = 30_PF
ns
ns
ns
µs
ns
µs
ns
Figure 2.54 and
Figure 2.55
C = 30_PF
ns
Page 67 of 107