S128 Datasheet, PDF (60/107 Pages) Renesas Technology Corp – Microcontroller

S128
2. Electrical Characteristics
Note 1. The differences among lines in 1-LSB resolution are normalized by this value.
Note 2. The drive capability of the PWM delay generation circuit output port is middle drive.
2.3.8
CAC Timing
Table 2.32 CAC timing
Parameter
CAC
CACREF input pulse width
t_Pcyc *¹ ≤ t_cac*²
t_Pcyc*¹ > t_cac*²
Symbol Min
Typ
t_CACREF 4.5 × t_cac + 3 × t_Pcyc -
5 × t_cac + 6.5 × t_Pcyc -
Test
Max Unit conditions
-
ns
-
-
ns
Note 1. t_Pcyc: PCLKB cycle.
Note 2. t_cac: CAC count clock source cycle.
2.3.9
SCI Timing
Table 2.33 SCI timing (1)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Symbol
Min
SCI
Input clock cycle
Asynchronous
t_Scyc
4
Clock synchronous
6
Input clock pulse width
Input clock rise time
Input clock fall time
Output clock cycle Asynchronous
Clock synchronous
t_SCKW
0.4
t_SCKr
-
t_SCKf
-
t_Scyc
6
4
Output clock pulse width
t_SCKW
0.4
Output clock rise time
1.8V or above t_SCKr
-
1.6V or above
-
Output clock fall time
1.8V or above t_SCKf
-
1.6V or above
-
Transmit data delay Clock
1.8V or above t_TXD
-
(master)
synchro
nous
1.6V or above
-
Transmit data delay Clock 2.7V or above
-
(slave)
synchro
nous
2.4V or above
-
1.8V or above
-
1.6V or above
-
Receive data setup Clock
2.7V or above t_RXS
45
time (master)
synchro
nous
2.4V or above
55
1.8V or above
90
1.6V or above
110
Receive data setup Clock 2.7V or above
40
time (slave)
synchro
nous
1.6V or above
45
Receive data hold Clock synchronous
t_RXH
5
time (master)
Receive data hold Clock synchronous
t_RXH
40
time (slave)
Note 1. t_Pcyc: PCLKB cycle.
Max
-
-
0.6
20
20
-
-
0.6
20
30
20
30
40
45
55
60
100
125
-
-
-
-
-
-
-
-
Unit^*1
t_Pcyc
Test conditions
Figure 2.41
t_Scyc
ns
ns
t_Pcyc
t_Scyc
ns
ns
ns
Figure 2.42
ns
ns
ns
ns
ns
R01DS0309EU0100 Rev.1.00
Mar 10, 2017
Page 60 of 107