S128 Datasheet, PDF (72/107 Pages) Renesas Technology Corp – Microcontroller

S128
2. Electrical Characteristics
2.3.11 IIC Timing
Table 2.37 IIC timing
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
Parameter
IIC
(standard mode,
SMBus)
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA input spike pulse removal
time
SDA input bus free time
(When wakeup function is disabled)
Symbol Min*¹
t_SCL
t_SCLH
t_SCLL
t_Sr
t_Sf
t_SP
6 (12) × t_IICcyc + 1300
3 (6) × t_IICcyc + 300
3 (6) × t_IICcyc + 300
-
-
0
t_BUF
3 (6) × t_IICcyc + 300
Max
-
-
-
1000
300
1 (4) × t_IICcyc
-
Test
Unit conditions
ns Figure 2.56
ns
ns
ns
ns
ns
ns
SDA input bus free time
t_BUF
3 (6) × t_IICcyc + 4 × t_Pcyc -
ns
(When wakeup function is enabled)
+ 300
START condition input hold time
t_STAH
t_IICcyc + 300
-
ns
(When wakeup function is disabled)
START condition input hold time
t_STAH
1 (5) × t_IICcyc + t_Pcyc + -
ns
(When wakeup function is enabled)
300
IIC
(Fast mode)
Repeated START condition input
setup time
STOP condition input setup time
Data input setup time
Data input hold time
SCL, SDA capacitive load
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA input spike pulse removal
time
t_STAS
t_STOS
t_SDAS
t_SDAH
C_b
t_SCL
t_SCLH
t_SCLL
t_Sr
t_Sf
t_SP
1000
1000
t_IICcyc + 50
0
-
6 (12) × t_IICcyc + 600
3 (6) × t_IICcyc + 300
3 (6) × t_IICcyc + 300
-
-
0
-
ns
-
ns
-
ns
-
ns
400
pF
-
ns
-
ns
-
ns
300
ns
300
ns
1 (4) × t_IICcyc ns
Figure 2.56
SDA input bus free time
t_BUF
3 (6) × t_IICcyc + 300
-
ns
(When wakeup function is disabled)
SDA input bus free time
t_BUF
3 (6) × t_IICcyc + 4 × t_Pcyc -
ns
(When wakeup function is enabled)
+ 300
START condition input hold time
t_STAH
t_IICcyc + 300
-
ns
(When wakeup function is disabled)
START condition input hold time
t_STAH
1(5) × t_IICcyc + t_Pcyc + -
ns
(When wakeup function is enabled)
300
Repeated START condition input
t_STAS
300
setup time
-
ns
STOP condition input setup time
t_STOS
300
-
ns
Data input setup time
t_SDAS
t_IICcyc + 50
-
ns
Data input hold time
t_SDAH
0
-
ns
SCL, SDA capacitive load
C_b
-
400
pF
Note: t_IICcyc: IIC internal reference clock (IICφ) cycle, t_Pcyc: PCLKB cycle
Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE
set to 1.
R01DS0309EU0100 Rev.1.00
Mar 10, 2017
Page 72 of 107