S128 Datasheet, PDF (65/107 Pages) Renesas Technology Corp – Microcontroller

S128
2. Electrical Characteristics
SSn
input
SCKn
CKPOL = 1
input
SCKn
CKPOL = 0
input
MISOn
output
MOSIn
input
(n = 0, 1, 9)
Figure 2.47
t_LEAD
t_SA
t_OH
t_OD
LSB OUT
(Last data)
MSB OUT
t_SU
t_H
MSB IN
DATA
t_Dr, t_Df
DATA
SCI simple SPI mode timing (slave, CKPH = 0)
t_TD
t_LAG
t_REL
LSB OUT
LSB IN
MSB OUT
MSB IN
Table 2.35 SCI timing (3)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
Parameter
Simple IIC
(Standard mode)
Simple IIC
(Fast mode)
SDA input rise time
SDA input fall time
SDA input spike pulse removal time
Data input setup time
Data input hold time
SCL, SDA capacitive load
SDA input rise time
SDA input fall time
SDA input spike pulse removal time
Data input setup time
Data input hold time
SCL, SDA capacitive load
Symbol
Min
t_Sr
-
t_Sf
-
t_SP
0
t_SDAS
250
t_SDAH
0
C_b*¹
-
t_Sr
-
t_Sf
-
t_SP
0
t_SDAS
100
t_SDAH
0
C_b*¹
-
Note: t_IICcyc: IIC internal reference clock (IICφ) cycle.
Note 1. Cb indicates the total capacity of the bus line.
Max
1000
300
4 × t_IICcyc
-
-
400
300
300
4 × t_IICcyc
-
-
400
Unit Test conditions
ns
Figure 2.48
ns
ns
ns
ns
pF
ns
Figure 2.48
ns
ns
ns
ns
pF
R01DS0309EU0100 Rev.1.00
Mar 10, 2017
Page 65 of 107