S128 Datasheet, PDF (6/107 Pages) Renesas Technology Corp – Microcontroller

S128
1. Overview
Table 1.3
System (2 of 2)
Feature
Resets
Low Voltage Detection (LVD)
Clock
Clock Frequency Accuracy
Measurement Circuit (CAC)
Interrupt Controller Unit (ICU)
Key interrupt function (KINT)
Low Power Mode
Register Write Protection
Memory Protection Unit (MPU)
Watchdog Timer (WDT)
Functional description
13 types of resets:
 RES pin reset
 Power-on reset
 Independent watchdog timer reset
 Watchdog timer reset
 Voltage monitor 0 reset
 Voltage monitor 1 reset
 Voltage monitor 2 reset
 SRAM parity error reset
 SRAM ECC error reset
 Bus master MPU error reset
 Bus slave MPU error reset
 CPU stack pointer error reset
 Software reset.
See section 5, Resets in User’s Manual.
The Low Voltage Detection (LVD) monitors the voltage level input to the VCC pin, and the
detection level can be selected using a software program. See section 7, Low Voltage
Detection (LVD) in User’s Manual.
 Main clock oscillator (MOSC)
 Sub-clock oscillator (SOSC)
 High-speed on-chip oscillator (HOCO)
 Middle-speed on-chip oscillator (MOCO)
 Low-speed on-chip oscillator (LOCO)
 Independent watchdog timer on-chip oscillator
 Clock out support.
See section 8, Clock Generation Circuit in User’s Manual.
The Clock Frequency Accuracy measurement circuit (CAC) checks the system clock
frequency with a reference clock signal by counting the number of pulses of the system clock
to be measured. The reference clock can be provided externally through a CACREF pin or
internally from various on-chip oscillators.
Event signals can be generated when the clock does not match or measurement ends.
This feature is particularly useful in implementing a fail-safe mechanism for home and
industrial automation applications.
See section 9, Clock Frequency Accuracy Measurement Circuit (CAC) in User’s Manual.
The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC
module. The ICU also controls NMI interrupts. See section 12, Interrupt Controller Unit (ICU) in
User’s Manual.
A key interrupt can be generated by setting the Key Return Mode register (KRM) and inputting
a rising or falling edge to the key interrupt input pins. See section 18, Key Interrupt Function
(KINT) in User’s Manual.
Power consumption can be reduced in multiple ways, including setting clock dividers, stopping
modules, selecting power control mode in normal operation, and transitioning to low power
modes. See section 10, Low Power Modes in User’s Manual.
The register write protection function protects important registers from being overwritten due to
software errors. See section 11, Register Write Protection in User’s Manual.
Four MPUs and a CPU stack pointer monitor function are provided for memory protection. See
section 14, Memory Protection Unit (MPU) in User’s Manual.
The Watchdog Timer (WDT) is a 14-bit down-counter. It can be used to reset the MCU when
the counter underflows because the system has run out of control and is unable to refresh the
WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. The
refresh-permitted period can be set to refresh the counter and used as the condition for
detecting when the system runs out of control. See section 24, Watchdog Timer (WDT) in
User’s Manual.
Independent Watchdog Timer (IWDT)
The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be
serviced periodically to prevent counter underflow. The IWDT provides functionality to reset
the MCU or to generate a non-maskable interrupt/interrupt for a timer underflow. Because the
timer operates with an independent, dedicated clock source, it is particularly useful in returning
the MCU to a known state as a fail safe mechanism when the system runs out of control. The
IWDT can be triggered automatically on a reset, underflow, refresh error, or by a refresh of the
count value in the registers. See section 25, Independent Watchdog Timer (IWDT) in User’s
Manual.
R01DS0309EU0100 Rev.1.00
Mar 10, 2017
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