S128 Datasheet, PDF (88/107 Pages) Renesas Technology Corp – Microcontroller

S128
2. Electrical Characteristics
Table 2.54 Power-on reset circuit and voltage detection circuit characteristics (2) (2 of 2)
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions
Power-on reset enable time
t_{W (POR)}
1
-
-
ms
Figure 2.65,
VCC = below 1.0 V
LVD operation stabilization time (after LVD is T_{d (E-A)}
-
-
300
μs
Figure 2.67,
enabled)
Figure 2.68
Hysteresis width (POR)
Hysteresis width (LVD0, LVD1 and LVD2)
V_PORH
-
V_LVH
-
-
-
-
-
-
110
-
60
-
100
-
60
-
50
-
40
-
60
-
mV
-
mV
LVD0 selected
V_{det1_0} to V_{det1_2} selected.
V_{det1_3} to V_{det1_9} selected.
V_{det1_A} to V_{det1_B} selected.
V_{det1_C} to V_{det1_F} selected.
LVD2 selected
Note 1. When OFS1.LVDAS = 0
Note 2. When OFS1.LVDAS = 1
Note 3. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection
levels V_POR, V_det0, V_det1, and V_det2 for the POR/LVD.
VCC
V_POR
1.0 V
t_VOFF
Internal reset signal
(active-low)
Figure 2.64 Voltage detection reset timing
t_det
t_det t_POR
VCC
V_POR
1.0 V
Internal reset signal
(active-low)
t_w(POR)
*1
Note:
t_det t_POR
t_w(por) is the time required for a power-on reset to be enabled while the external power VCC is being
held below the valid voltage (1.0 V).
When VCC turns on, maintain t_w(por) for 1.0 ms or more.
Figure 2.65 Power-on reset timing
R01DS0309EU0100 Rev.1.00
Mar 10, 2017
Page 88 of 107