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S128 Datasheet, PDF (50/107 Pages) Renesas Technology Corp – Microcontroller
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S128
2. Electrical Characteristics
Table 2.18 Operation frequency in low-speed mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Operation
frequency
System clock (ICLK)*1, *2, *4
Peripheral module clock (PCLKB)*4
1.8 to 5.5 V
1.8 to 5.5 V
Peripheral module clock (PCLKD)*3, *4 1.8 to 5.5 V
Symbol Min
Typ
f
0.032768
-
-
-
-
-
Max*5
1
1
1
Unit
MHz
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory.
Note 2. The frequency accuracy of ICLK must be ±3.5% during programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the A/D converter is in use.
Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK,
PCLKB, and PCLKD.
Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of
guaranteed operation, see Table 2.21, Clock timing.
Table 2.19 Operation frequency in low-voltage mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Operation
frequency
System clock (ICLK)*1, *2, *4
Peripheral module clock (PCLKB)*4
Peripheral module clock (PCLKD)*3, *4
1.6 to 5.5 V
1.6 to 5.5 V
1.6 to 5.5 V
Symbol Min
Typ
f
0.032768
-
-
-
-
-
Max*5
4
4
4
Unit
MHz
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for
programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz.
A non-integer frequency such as 1.5 MHz cannot be set.
Note 2. The frequency accuracy of ICLK must be ±3.5% during programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D
converter is in use.
Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK,
PCLKB, and PCLKD.
Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of
guaranteed operation, see Table 2.21, Clock timing.
Table 2.20 Operation frequency in Subosc-speed mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Symbol Min
Typ
Max
Unit
Operation
frequency
System clock (ICLK)*1, *3
Peripheral module clock (PCLKB)*3
1.8 to 5.5 V
f
1.8 to 5.5 V
27.8528 32.768 37.6832
kHz
-
-
37.6832
Peripheral module clock (PCLKD)*2, *3 1.8 to 5.5 V
-
-
37.6832
Note 1. Programming and erasing the flash memory is not possible.
Note 2. The 14-bit A/D converter cannot be used.
Note 3. See section 8, Clock Generation Circuit in User’s Manual for the relationship between ICLK, PCLKB, and PCLKD
frequencies.
R01DS0309EU0100 Rev.1.00
Mar 10, 2017
Page 50 of 107
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