M16C62_N Datasheet, PDF (41/621 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY

Memory Space Expansion Functions
Mitsubishi microcomputers
M16C / 62 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The data bank register is made up of the bank selection bits (bits 5 through 3) and the offset bit (bit 2). The
bank selection bits are used to set a bank number for accessing data lying between 4000016 and
BFFFF16. Assigning 1 to the offset bit provides the means to set offsets covering 4000016.
Figure 1.8.5 shows the memory location and chip select areas in expansion mode 2.
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The area relevant to CS0 ranges from 4000016 through FFFFF16. As for the area from 4000016 through
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BFFFF16, the bank number set by use of the bank selection bits are output from the output terminals CS3
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- CS1 only in accessing data. In fetching a program, bank 7 (1112) is output from CS3 - CS1. As for the
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area from C000016 through FFFFF16, bank 7 (1112) is output from CS3 - CS1 without regard to accessing
data or to fetching a program.
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In accessing an area irrelevant to CS0, a chip select signal CS3 (400016 - 7FFF16), CS2 (800016 -
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27FFF16), and CS1 (2800016 - 3FFFF16) is output depending on the address as in the past.
Figure 1.8.6 shows an example of connecting the MCU with a 4-M byte ROM and to a 128-K byte SRAM.
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Connect the chip select of 4-M byte ROM with CS0. Connect M16C’s CS3, CS2, and CS1 with address
inputs AD21, AD20, and AD19 respectively. Connect M16C’s output A19 with address input AD18. Fig-
ure 1.8.7 shows the relationship between addresses of the 4-M byte ROM and those of M16C.
In this mode, memory is
banked every 512 K bytes,
so that data access in differ-
ent banks requires switching
over banks. However, data
on bank boundaries when
offset bit = 0 can be ac-
cessed successively by set-
ting the offset bit to 1, be-
cause in which case the
memory address is offset by
4000016. For example, two
bytes of data located at ad-
dresses 0FFFFF16 and
10000016 of 4-Mbyte ROM
can be accessed succes-
sively without having to
change the bank bit by set-
ting the offset bit to 1 and
then accessing addresses
07FFFF16 and 80000016.
On the other hand, the
SRAM’s chip select assumes
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that CS0=1 (not selected)
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and CS2=0 (selected), so
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connect CS0 with S2 and
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CS2 with S1. If the SRAM
doesn’t have a bipolar chip
select input terminal, decode
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CS0 and CS2 externally.
An example of connecting the MCU with
external memories in expansion mode 2
(M30622MC, Microprocessor mode)
D0 to D7
A0 to A16
A17
A19
8
DQ0 to DQ7
17
AD0 to AD16
AD17
AD18
CS1
CS2
CS3
RD
CS0
AD19
AD20
AD21
OE
CS
WR
DQ0 to DQ7
AD0 to AD16
OE
S2
S1
W
Note: If only one chip select terminal (S1 or S2) is present,
decoding by use of an external circuit is required.
Figure 1.8.6. An example of connecting the MCU with external
memories in expansion mode 2
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