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M16C62_N Datasheet, PDF (40/621 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY
Memory Space Expansion Functions
Mitsubishi microcomputers
M16C / 62 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Expansion mode 2
In expansion mode 2, the data bank register (0000B16) goes effective. Figure 1.8.4 shows the data bank
register.
Data bank register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DBR
Address
000B16
When reset
0016
Bit symbol
Bit name
Description
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
OFS
Offset bit
0: Not offset
1: Offset
BSR
Bank selection bits
b5 b4 b3
0 0 0: Bank 0
0 1 0: Bank 2
1 0 0: Bank 4
1 1 0: Bank 6
b5 b4 b3
0 0 1: Bank 1
0 1 1: Bank 3
1 0 1: Bank 5
1 1 1: Bank 7
RW
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Figure 1.8.4. Data bank register
Expansion mode 2 (memory space = 4M bytes for PM15 = 1, PM14 = 1)
0000016
0040016
XXXXX16
0400016
Memory
expansion mode
SFR area
Internal RAM area
Internal area reserved
0800016
Microprocessor
mode
SFR area
Internal RAM area
Internal area reserved
CS3(16K bytes)
CS2(128K bytes)
2800016
CS1 (96K bytes)
4000016
External area
External area
CS0
D000016
Internal area reserved
YYYYY16
Internal ROM area
Memory expansion mode:
512K bytes x 7banks +
256K bytes
Microprocessor mode:
512K bytes x 8banks
FFFFF16
Type No.
M30622M4
M30620M8
M30620MA
Address XXXXX16
00FFF16
02BFF16
02BFF16
Address YYYYY16
F800016
F000016
E800016
M30620MC/EC
M30622M8/E8
M30622MA
M30622MC
M30624MG/FG
02BFF16
013FF16
017FF16
017FF16
053FF16
E000016
F000016
E800016
E000016
C000016
Addresses from 4000016 through BFFFF16
Bank 7 in fetching a program
A bank selected by use of the bank selection
bits in accessing data
Addresses from C000016 through FFFFF16
Bank 7 invariably
Bank number is output to CS3 to CS1
Note 1: These memory maps show an instance in which PM13 is set to 0; but in the case of M30624MG/FG, they
show an instance in which PM13 is set to 1.
Note 2: The memory maps in single-chip mode are omitted.
Figure 1.8.5. Memory location and chip select area in expansion mode 2
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