M16C62_N Datasheet, PDF (349/621 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY

Clock-Synchronous Serial I/O
Mitsubishi microcomputers
M16C / 62 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.4.2 Operation of Serial I/O (transmission in clock-synchronous serial I/O mode)
In transmitting data in clock-synchronous serial I/O mode, choose functions from those listed in Table
2.4.1. Operations of the circled items are described below. Figure 2.4.7 shows the operation timing, and
Figures 2.4.8 and 2.4.9 show the set-up procedures.
Table 2.4.1. Choosed functions
Item
Set-up
Item
Set-up
Transfer clock
source
O Internal clock (f1 / f8 / f32)
External clock (CLKi pin)
Transmission
interrupt factor
O Transmission buffer empty
Transmission complete
CTS function
O CTS function enabled
CTS function disabled
Output transfer clock _{O Not selected}
to multiple pins
(Note 1)
Selected
CLK polarity
Output transmission data at CTS / RTS
O the falling edge of the
separation function
transfer clock
(Note 2)
Output transmission data at Data logic select
the rising edge of the
function
transfer clock
(Note 3)
O _{Pin shared by CTS and RTS}
CTS and RTS separated
O No reverse
Reverse
Transfer clock
O LSB first
MSB first
TXD, RXD I/O
polarity reverse bit
(Note 3)
O No reverse
Reverse
Note 1: This can be selected only when UART1 is used in combination with the internal clock. When this function is
_______ _______
_______ _______
selected, neither UART1 CTS/RTS function, nor UART0 CTS/RTS separation function can be utilized. Set the
_______ _______
UART1 CTS/RTS disable bit to “1”.
_______ _______
Note 2: UART0 only. (UART1 CTS/RTS function cannot be used when this function is selected.)
Note 3: UART2 only.
Operation (1) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit
buffer register makes data transmissible status ready.
________
_______
(2) When input to the CTSi pin goes to “L” level, transmission starts (the CTSi pin must be
controlled on the reception side).
(3) In synchronization with the first falling edge of the transfer clock, transmission data held in the
UARTi transmit buffer register is transmitted to the UARTi transmit register. At this time, the
UARTi transmit interrupt request bit goes to “1”. Also, the first bit of the transmission data is
transmitted from the TxDi pin. Then the data is transmitted bit by bit from the lower order in
synchronization with the falling edges.
(4) When transmission of 1-byte data is completed, the transmit register empty flag goes to “1”,
which indicates that transmission is completed. The transfer clock stops at “H” level.
(5) If the next transmission data is set in the UARTi transmit buffer register while transmission is
in progress (before the eighth bit has been transmitted), the data is transmitted in succession.
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