M16C62_N Datasheet, PDF (206/621 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY

Timing (VCC=5V)
Mitsubishi microcomputers
M16C / 62 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25^oC, CM15 = “1” unless
otherwise specified)
Table 1.26.21. Memory expansion mode and microprocessor mode
(with wait, accessing external memory, multiplex bus area selected)
Symbol
Parameter
td(BCLK-AD) Address output delay time
Measuring condition
Standard
Min. Max.
25
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
4
(Note)
(Note)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
Chip select output delay time
Chip select output hold time (BCLK standard)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
RD signal output delay time
RD signal output hold time
25
4
(Note)
(Note)
25
0
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
25
Figure 1.26.1
0
40
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-ALE)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)
ALE signal output delay time (BCLK standard)
4
(Note)
(Note)
25
th(BCLK-ALE) ALE signal output hold time (BCLK standard)
td(AD-ALE) ALE signal output delay time (Address standard)
–4
(Note)
th(ALE-AD) ALE signal output hold time (Adderss standard)
30
td(AD-RD)
Post-address RD signal output delay time
0
td(AD-WR) Post-address WR signal output delay time
tdZ(RD-AD) Address output floating start time
Note: Calculated according to the BCLK frequency as follows:
0
8
10 ⁹
th(RD – AD) =
f(BCLK) X 2
[ns]
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10 ⁹
th(WR – AD) =
f(BCLK) X 2
[ns]
10 ⁹
th(RD – CS) =
f(BCLK) X 2
[ns]
10 ⁹
th(WR – CS) =
f(BCLK) X 2
[ns]
td(DB – WR) =
10 ^{9 X 3}
f(BCLK) X 2 ^{– 40} [ns]
10 ⁹
th(WR – DB) =
f(BCLK) X 2
[ns]
10 ⁹
td(AD – ALE) = _{f(BCLK) X 2 – 25 [ns]}
191