M16C62_N Datasheet, PDF (204/621 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY

Timing (VCC=5V)
Mitsubishi microcomputers
M16C / 62 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25^oC, CM15 = “1” unless
otherwise specified)
Table 1.26.19. Memory expansion mode and microprocessor mode (no wait)
Symbol
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
Parameter
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip select output delay time
Measuring condition
Standard
Min. Max.
25
4
0
0
25
th(BCLK-CS) Chip select output hold time (BCLK standard)
4
td(BCLK-ALE)
th(BCLK-ALE)
ALE signal output delay time
ALE signal output hold time
25
Figure 1.26.1 _{– 4}
td(BCLK-RD) RD signal output delay time
25
th(BCLK-RD) RD signal output hold time
0
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
25
0
40
4
(Note1)
th(WR-DB)
Data output hold time (WR standard)(Note2)
0
Note 1: Calculated according to the BCLK frequency as follows:
10 ⁹
td(DB – WR) =
– 40
f(BCLK) X 2
[ns]
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
DBi
t = –CR X ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC)
= 6.7ns.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R
C
189