M16C62_N Datasheet, PDF (157/621 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY

UART2 Special Mode Register
Mitsubishi microcomputers
M16C / 62 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In the first place, the control bits related to the I²C bus (simplified I²C bus) interface are explained.
Bit 0 of the UART special mode register (037716) is used as the I²C mode selection bit.
Setting “1” in the I²C mode select bit (bit 0) goes the circuit to achieve the I²C bus (simplified I²C bus)
interface effective.
Table 1.19.9 shows the relation between the I²C mode select bit and respective control workings.
Since this function uses clock-synchronous serial I/O mode, set this bit to “0” in UART mode.
P70 through P72 conforming to the simplified I ²C bus
P70/TxD2/SDA
P71/RxD2/SCL
P72/CLK2
Noize
Filter
Timer
Selector
I/O
UART2
IICM=1
delay
IICM=0
Timer
DQ
T Arbitration
IICM=1
IICM=0
Start condition detection
Stop condition detection
Transmission
register
UART2
Reception register
UART2
S
R ^Q Bus busy
IICM=0
IICM=1
UART2 transmission/
NACK interrupt
request
IICM=0
IICM=1
UART2 reception/ACK
interrupt request
DMA1 request
Falling edge
detection
L-synchronous
output enabling bit
NACK
DQ
T
Noize
Filter
Noize
Filter
I/O
R
Q
Data bus
Selector
(Port P71 output data latch)
UART2 Internal clock
IICM=1
CLK
IICM=1
External clock
IICM=0
UART2
DQ
T
9th pulse
ACK
IICM=1
Bus collision
detection
IICM=0
Bus collision/start, stop
condition detection
interrupt request
Port reading
UART2 IICM=0
Selector
I/O
* With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P71 of the direction register.
Timer
To DMA0, DMA1
To DMA0
Figure 1.19.27. Functional block diagram for I²C mode
Figure 1.19.27 shows the functional block diagram for I²C mode. Setting “1” in the I²C mode selection bit
(IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock input-
output terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission output,
so the SDA output changes after SCL fully goes to “L”. An attempt to read Port P71 (SCL) results in
getting the terminal’s level regardless of the content of the port direction register. The initial value of SDA
transmission output in this mode goes to the value set in port P70. The interrupt factors of the bus collision
detection interrupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the start/stop
condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment detection
interrupt respectively.
The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA
terminal (P70) is detected with the SCL terminal (P71) staying “H”. The stop condition detection interrupt
refers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected with the SCL
terminal (P71) staying “H”. The bus busy flag (bit 2 of the UART2 special mode register) is set to “1” by the
start condition detection, and set to “0” by the stop condition detection.
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