HYB18L256160B Datasheet, PDF (9/58 Pages) Qimonda AG – DRAMs for Mobile Applications 256-Mbit Mobile-RAM

Data Sheet
2.2
Register Definition
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
2.2.1
Mode Register
The Mode Register is used to define the specific mode of operation of the Mobile-RAM. This definition includes the selection
of a burst length (bits A0-A2), a burst type (bit A3), a CAS latency (bits A4-A6), and a write burst mode (bit A9). The Mode
Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored
information until it is programmed again or the device loses power.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any
subsequent operation. Violating either of these requirements results in unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
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Field Bits
WB 9
CL [6:4]
BT 3
BL [2:0]
Type
w
w
w
w
Description
TABLE 5
Mode Register Definition (BA[1:0] = 00_B)
Write Burst Mode
0_B Burst Write
1_B Single Write
CAS Latency
010_B 2
011_B 3
Note: All other bit combinations are RESERVED.
Burst Type
0_B Sequential
1_B Interleaved
Burst Length
000_B 1
001_B 2
010_B 4
011_B 8
111_B full page (Sequential burst type only)
Note: All other bit combinations are RESERVED.
Rev. 1.73, 2006-09
9
01302004-CZ2R-J9SE