HYB18L256160B Datasheet, PDF (20/58 Pages) Qimonda AG – DRAMs for Mobile Applications 256-Mbit Mobile-RAM

Data Sheet
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
Parameter
Symbol
TABLE 12
Timing Parameters for READ
- 7.5
Units Note
min.
max.
Access time from CLK
CL = 3 t_AC
—
5.4
ns
—
CL = 2 t_AC
—
6.0
ns
DQ low-impedance time from CLK
t_LZ
1.0
—
ns
—
DQ high-impedance time from CLK
t_HZ
3.0
7.0
ns
Data out hold time
t_OH
2.5
—
ns
—
DQM to DQ High-Z delay (READ Commands)
t_DQZ
—
2
t_CK
—
ACTIVE to ACTIVE command period
t_RC
67
—
ns
1)
ACTIVE to READ or WRITE delay
ACTIVE to PRECHARGE command period
PRECHARGE command period
t_RCD
19
t_RAS
45
t_RP
19
—
100k
—
ns
1)
ns
1)
ns
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
During READ bursts, the valid data-out element from the starting column address is available following the CAS latency after
the READ command. Each subsequent data-out element is valid nominally at the next positive clock edge. Upon completion
of a READ burst, assuming no other READ command has been initiated, the DQs go to High-Z state.
Figure 13 and Figure 14 show single READ bursts for each supported CAS latency setting.
FIGURE 13
Single READ Burst (CAS Latency = 2)
&/ .
&R PP DQG $&7 
$GG UHVV 
%D $ 
5R Z[ 
$$3 5R Z[ 
'4 
W_{5& ' }
12 3 
W_{5$ 6}
W_{5& }
5( $'
12 3 
12 3 
12 3 
35( 
W₅ _3
123 
$&7
%D$ 
&R OQ
'LV$ 3
&/   
3UH $OO
$3
3UH% DQN$ 
%D$ 
5R ZE 
5R ZE 
'2 Q '2 Q   '2 Q   '2 Q  
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'2 Q 'D WD2XWIURP FROX P QQ
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VX EVHTXHQ WHOH PH QWV RI'D WD2 XWDUHS URYLG HG LQ WKHSURJUDPPH GRUGHUIROOR ZLQJ '2 Q
'R Q W&D UH 
Rev. 1.73, 2006-09
20
01302004-CZ2R-J9SE