HYB18L256160B Datasheet, PDF (3/58 Pages) Qimonda AG – DRAMs for Mobile Applications 256-Mbit Mobile-RAM

1
Overview
Data Sheet
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
1.1
Features
• 4 banks × 4 Mbit × 16 organization
• Fully synchronous to positive clock edge
• Four internal banks for concurrent operation
• Programmable CAS latency: 2, 3
• Programmable burst length: 1, 2, 4, 8 or full page
• Programmable wrap sequence: sequential or interleaved
• Programmable drive strength
• Auto refresh and self refresh modes
• 8192 refresh cycles / 64 ms
• Auto precharge
• Commercial (0°C to +70°C) and Extended (-25°C to +85°C) operating temperature range
• 54-ball P-VFBGA package (12.0 × 8.0 × 1.0 mm)
Power Saving Features
• Low supply voltages: V_DD = 1.65V to 1.95V, V_DDQ = 1.65V to 1.95V
• Optimized self refresh (I_DD6) and standby currents (I_DD2 / I_DD3)
• Programmable Partial Array Self Refresh (PASR)
• Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor
• Power-Down and Deep Power Down modes
Part Number Speed Code
Speed Grade
Access Time (t_ACmax)
Clock Cycle Time (t_CKmin)
CL = 3
CL = 2
CL = 3
CL = 2
TABLE 1
Performance
- 7.5
Unit
133
MHz
5.4
ns
6.0
ns
7.5
ns
9.5
ns
Item
Banks
Rows
Columns
Addresses
BA0, BA1
A0 - A12
A0 - A8
TABLE 2
Memory Addressing Scheme
Rev. 1.73, 2006-09
3
01302004-CZ2R-J9SE