HYB18L256160B Datasheet, PDF (29/58 Pages) Qimonda AG – DRAMs for Mobile Applications 256-Mbit Mobile-RAM

Data Sheet
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
Parameter
Symbol
TABLE 13
Timing Parameters for WRITE
- 7.5
Units
Note
min.
max.
DQ and DQM input setup time
DQ input hold time
DQM input hold time
t_IS
1.5
—
t_IH
0.8
—
0.5
—
ns
—
ns
—
ns
—
DQM write mask latency
t_DQW
0
—
t_CK
—
ACTIVE to ACTIVE command period
t_RC
67
—
ns
1)
ACTIVE to READ or WRITE delay
t_RCD
19
—
ns
1)
ACTIVE to PRECHARGE command period t_RAS
45
100k
ns
1)
WRITE recovery time
t_WR
14
—
ns
1)
PRECHARGE command period
t_RP
19
—
ns
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
FIGURE 25
WRITE Burst (CAS Latency = 2)
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Rev. 1.73, 2006-09
29
01302004-CZ2R-J9SE