HYB18L256160B Datasheet, PDF (50/58 Pages) Qimonda AG – DRAMs for Mobile Applications 256-Mbit Mobile-RAM

Data Sheet
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
Parameter
Symbol
- 7.5
Unit Note^1)2)3)4)
min.
max.
DQM write mask latency
t_DQW
0
—
t_CK
—
ACTIVE to ACTIVE command period
t_RC
67
—
ns
8)
ACTIVE to READ or WRITE delay
t_RCD
19
—
ns
8)
ACTIVE bank A to ACTIVE bank B delay
t_RRD
15
—
ns
8)
ACTIVE to PRECHARGE command period
t_RAS
45
100k
ns
8)
WRITE recovery time
t_WR
14
—
ns
9)
PRECHARGE command period
t_RP
19
—
ns
8)
Refresh period (8192 rows)
t_REF
—
64
ms —
Self refresh exit time
t_SREX
1
—
t_CK
—
1) 0 °C ≤ T_C ≤ 70 °C (comm.); -25 °C ≤ T_C ≤ 85 °C (ext.); V_DD = V_DDQ = 1.65V to 1.95V;
2) All parameters assumes proper device initialization.
3) AC timing tests measured at 0.9 V.
4) The transition time t_T is measured between V_IH and V_IL; all AC characteristics assume t_T = 1 ns.
5) Specified t_AC and t_OH parameters are measured with a 30 pF capacity load only as shown in Figure 47.
6) If t_T(CLK) > 1 ns, a value of (t_T/2 - 0.5) ns has to be added to this parameter.
7) If t_T > 1 ns, a value of (t_T - 1) ns has to be added to this parameter.
8) These parameter account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
9) The write recovery time of t_WR = 14 ns allows the use of one clock cycle for the write recovery time when f_CK ≤ 72 MHz. With f_CK > 72 MHz
two clock cycles for t_WR are mandatory. Qimonda Technologies recommends to use two clock cycles for the write recovery time in all
applications.
FIGURE 47
Measurement Conditions for t_AC and t_OH
I/O
30 pF
Rev. 1.73, 2006-09
50
01302004-CZ2R-J9SE